Micron Technology Incorporated

Li-Te Chang

Zhenming Zhou

Murong Lang

Zhengang Chen

Yu-Chung Lien

Seungjune Jeon

Zhongguang Xu

Charles See Yeung Kwong

Lei Lin

Peng Zhang

Vamsi Pavan Rayaprolu

Ting Luo

Michael G Miller

Wei Wang

Aaron Lee

Hanping Chen

A processing device in a memory sub-system determines one or more read margin levels associated with the memory device. A machine learning model is applied to the one or more read margin levels to generate a read margin prediction value associated with the memory device. Based on the margin prediction value, the memory device is assigned to a selected bin of a set of bins. A media scan operation is executed on the memory device in accordance with a scan frequency associated with the selected bin.

Adaptive scanning of memory devices with supervised learning

Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform adaptive read level threshold voltage operations. The controller determines a first read level offset associated with reading a first set of data from a first level using a first read level of a plurality of read levels. The controller applies the first read level offset to a machine learning model to estimate a second read level offset, associated with reading a second set of data from a second level of the plurality of levels, using a second read level of the plurality of read levels. The controller updates, based on the first read level offset and the estimated second read level offset, a look-up table that includes a set of read level offsets used to read data from the plurality of levels of the individual component.

Model based error avoidance

In some implementations, a memory device may determine that a power loss has occurred. The memory device may determine a last written page (LWP) location associated with an LWP of a block of a memory of the memory device. The memory device may determine one of: a word line group (WLG) associated with the LWP location and at least one WLG-dependent offset associated with the WLG, or a partial block (PB) fill ratio associated with the LWP location and at least one PB-fill-ratio-dependent offset associated with the PB fill ratio. The memory device may perform a power loss error detection procedure based on one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset by applying the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset to at least one read reference voltage.

Power loss error detection using partial block handling

A block of a memory device is identified. A threshold voltage offset corresponding to a wordline associated with the block is identified based on a threshold voltage offset table. The threshold voltage offset table corresponds to at least one of: a value of a media state metric associated with the block, a wordline group of the wordline, or a difference between the wordline and a boundary wordline of the block. A read operations is performed on the block using a read level voltage modified by the threshold voltage offset, wherein the read level voltage is associated with the block.

Error avoidance for partially programmed blocks of a memory device

A system includes a memory device with multiple cells and a processing device to perform operations including: identifying a group of wordlines, each connected to a subset of cells, and assigning a specified charge loss classification value to that group. The operations can also include selecting a page level, selecting a first set of cells, determining, for the first set of cells, a value of a first data state metric, identifying a second set of cells charged to a specified charge state, and determining a value of a second data state metric. The operations can also include maintaining a skew counter of the second data state metric, identifying and updating a read reference voltage offset, as well as applying the updated read reference voltage offset in a read operation.

Dynamic read calibration

A processing device in a memory sub-system detects an occurrence of a data integrity check trigger event in the memory sub-system, and in response, identifies a memory die of a plurality of memory dies in the memory sub-system. The processing device further determines a read margin associated with a first distribution of memory cells of the identified memory die, and determines an adaptive scan frequency for the identified memory die based on the read margin associated with the first distribution of memory cells.

Adaptive integrity scan in a memory sub-system

A method for receiving a request for performing a programming operation on one or more memory blocks of a memory device, identifying a value of a media endurance metric associated with the one or more memory blocks, determining a programming voltage offset corresponding to the value of the media endurance metric, and performing, using the programming voltage offset, the programming operation on the one or more memory blocks. The method further includes identifying a program-verify voltage level associated with the one or more memory blocks, determining a program-verify voltage offset associated with the program-verify voltage level and the value of the media endurance metric, and performing, using the program-verify voltage level and the program-verify voltage offset, a program-verify operation on the one or more memory blocks.

Modification of program voltage level with read or program-verify adjustment for improving reliability in memory devices

A first page read on the first memory page utilizing a first trim value is performed responsive to initiating a memory page scan on a first memory page of a plurality of memory pages. Whether a first data state metric associated with the first page read satisfies a first threshold criterion is determined. A second page read on the first memory page utilizing a second trim value is performed responsive to determining that the first data state metric satisfies the first threshold criterion. Whether a second data state metric associated with the second page read satisfies a second threshold criterion is determined. The second trim value to perform subsequent page reads during memory page scans is selected responsive to determining that the second data state metric does not satisfy the first threshold criterion.

Dynamic read level trim selection for scan operations of memory devices

Methods, systems, and devices for read window management in a memory system are described. A memory system may determine, for a set of memory cells, a first value for a read window that is associated with a set of one or more threshold voltages each representing a different multi-bit value. The memory system may then use the first value for the read window to predict a second value for the read window. Based on the second value for the read window, the memory system may predict an error rate for the set of memory cells. The memory system may then set a value for an offset for a threshold voltage of the set of one or more threshold voltages based on the error rate.

Read window management in a memory system

An example method of performing memory access operations comprises: receiving a request to perform a memory access operation with respect to a set of memory cells connected to a wordline of a memory device; identifying a block family associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; responsive to determining that the value of the data state metric satisfies a threshold criterion, determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.

Adaptive error avoidance in the memory devices

A processing device in a memory sub-system determines whether a media endurance metric associated with a memory block of a memory device satisfies one or more conditions. In response to the one or more conditions being satisfied, one or more read margin levels corresponding to a page type associated with the memory device are determined. A machine learning model is applied to the one or more read margin levels to generate a margin prediction value based on the page type and a wordline group associated with the memory device. Based on the margin prediction value, the memory device is assigned to a selected bin of a set of bins. A media scan operation is executed on the memory device in accordance with a scan frequency associated with the selected bin.

An example system can include a memory device and a processing device. The memory device can include a group of memory cells. The processing device can be coupled to the memory device. The processing device can be configured to determine a distance of a memory die from a center of a memory component. The processing device can be configured to perform a read disturb operation on the memory die based on the determined distance use a first voltage window for a set of memory cells of the group of memory cells during a first time period.

Read disturb management

A read command is received by a processing device coupled to a memory device. The read command specified a logical address. The processing device translates the logical address into a physical address of a physical block of the memory device, wherein the physical address specifies a wordline and a memory device die. Responsive to determining that the physical block is partially programmed, the processing device identifies a threshold voltage offset associated with the wordline. The processing device computes a modified threshold voltage by applying the threshold voltage offset to a read level associated with the memory device die. The processing device reads the data from the physical block using the modified threshold voltage.

Systems, methods, and apparatus related to memory devices. In one approach, a cross-point memory array includes memory cells. A media controller reads one or more first memory cells and determines a read status. The read status indicates an error when reading the first memory cells. In response to this error, the controller refreshes the first memory cells. The controller uses the read status to determine zero-to-one failures associated with the first memory cells. If a number of these failures exceeds a threshold, then a refresh is applied to neighboring memory cells of the first memory cells. The physical addresses for the neighboring memory cells are determined by the controller from the physical addresses for the first memory cells.

Refresh of neighboring memory cells based on read status

A processing device of a memory sub-system is configured to determine a current refresh frequency associated with the memory device, the current refresh frequency specifying a rate of performing refresh operations on data stored at the memory device; compute an updated refresh frequency by updating the current refresh frequency based on a criterion reflecting a result of comparing one or more operating parameters of the memory device to their respective threshold values; and perform a refresh operation on data stored at the memory device according to the updated refresh frequency.

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Li-Te Chang