Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Li-Shiun Chen

Chia-Pin Lin

Hsien-Chin Lin

Shyue-Shyh Lin

Tian-Choy Gan

Shin Hsien Liao

Hun-Jan Tao

Ming-Ching Chang

Li-Te S Lin

Huan-Just Lin

Kuang-Yuan Hsu

Nien-Chung Li

Fang Wen Tsai

Shun Wu Lin

Ming-Shing Chen

Hui-Ling Huang

Jim Cy Huang

Hsin Tai

Yung-Hog Chiu

Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including first and second poly gates, forming an inter-level dielectric (ILD) over the substrate, performing a chemical mechanical polishing on the ILD to expose the first and second poly gates, forming a mask to protect the first poly gate of the first gate structure, removing the second poly gate thereby forming a first trench, removing the mask, partially removing the first poly gate thereby forming a second trench, forming a work function metal layer partially filling the first and second trenches, forming a fill metal layer filling a remainder of the first and second trenches, and removing the metal layers outside the first and second trenches.

Hybrid gate process for fabricating FinFET device

Hybrid gate process for fabricating finfet device

A method for fabricating a integrated circuit is disclosed. An exemplary method includes providing a substrate; forming a hard mask layer over the substrate; forming a patterned photoresist layer over the hard mask layer, such that portions of the hard mask layer are exposed; performing a dry etching process to remove the exposed portions of the hard mask layer; removing the patterned photoresist layer using at least one of a nitrogen plasma ashing and a hydrogen plasma ashing; and performing a wet etching process to remove remaining portions of the hard mask layer.

Method for metal gate N/P patterning

A method for manufacturing MOS transistor with hybrid hard mask includes providing a substrate having a dielectric layer and a polysilicon layer thereon, forming a hybrid hard mask having a middle hard mask and a spacer hard mask covering sidewalls of the middle hard mask on the polysilicon layer, performing a first etching process to etch the polysilicon layer and the dielectric layer through the hybrid hard mask to form a gate structure, performing a second etching process to form recesses in the substrate at two sides of the gate structure, and performing a SEG process to form epitaxial silicon layers in each recess.

Method for manufacturing MOS transistors utilizing a hybrid hard mask

A method for compensating CD variations across a semiconductor process wafer surface in a plasma etching process including a semiconductor wafer having a process surface comprising patterned features; carrying out a first plasma etching process wherein the semiconductor wafer is heated to at least two selectively controllable temperature zones; determining a first dimensional variation of etched features with respect to reference dimensions over predetermined areas of the process surface including the two selectively controllable temperature zones; determining operating temperatures for the two selectively controllable temperature zones to achieve a targeted dimensional variation change in the first dimensional variation to achieve a desired second dimensional variation; plasma etching the process surface to the desired operating temperatures; and, determining an actual dimensional variation change for use in at least one subsequent plasma etching process.

Dynamic feed forward temperature control to achieve CD etching uniformity

Growing community of inventors

Hsinchu, Taiwan

Li-Shiun Chen