United Microelectronics Corp.

Li-Ping Huang

Chun-Hsien Huang

Yu-Tse Kuo

Shu-Ru Wang

Chun-Yen Tseng

Ching-Cheng Lung

Meng-Ping Chuang

Chia-Wei Huang

Yung-Feng Cheng

Yi-Wei Chen

Ching-Wen Hung

Chien-Hung Zordius Chen

Shih-Fang Tzou

Chih-Sen Huang

Hsin-Chih Yu

Yu-Fang Chen

Chien-Hung Chen

Jia-Rong Wu

Yi-Ting Wu

Jen-Yu Wang

Chun-Chieh Chang

Tzu-Feng Chang

The present invention provides a spin-orbit torque magnetic random access memory (SOT-MRAM) circuit, including a read transistor pair with two read transistors in parallel, a write transistor pair with two write transistors in parallel, a SOT memory cell with a magnetic tunnel junction (MTJ) and a SOT layer, wherein one end of the MTJ is connected to the source of the read transistor pair and the other end of the MTJ is connected to the SOT layer, and one end of the SOT layer is connected to a source line and the other of the SOT layer is connected to the source of the write transistor pair, a read bit line is connected to the drain of the read transistor pair and a write bit line is connected to the drain of the read transistor.

Spin-orbit torque magnetic random access memory circuit and layout thereof

The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Layout pattern of static random access memory and the forming method thereof

The present invention provides a layout pattern of static random access memory, comprising a PU(first pull-up transistor), a PU(second pull-up transistor), a PDA (first pull-down transistor), a PDB (second pull-down transistor), a PDA (third pull-down transistor), a PDB (fourth pull-down transistor), a PGA (first access transistor), a PGB (second access transistor), a PGA (third access transistor) and a PGB (fourth access transistor) located on the substrate. The PDA and the PDB are connected in parallel with each other, the PDA and the PDB are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

Layout pattern of static random access memory

A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

Layout of semiconductor memory device

The invention provides a semiconductor layout pattern, the semiconductor layout pattern includes a substrate, a plurality of ternary content addressable memories (TCAM) are arranged on the substrate, the layout of at least two TCAM is mirror symmetric with each other along an axis of symmetry, and the two TCAM are connected to the same search line (SL) together.

Semiconductor layout pattern and forming method thereof

A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL), a first pull-down transistor (PD), a second (PL), and a second pull-down transistor (PD) on the substrate, and a first pass gate transistor (PGA), a second pass gate transistor (PGB), a third pass gate transistor (PGA) and a fourth pass gate transistor (PGB), wherein the PGA and the PGB comprise a first fin structure, the PGA and the PGB comprise a second fin structure, a first local interconnection layer disposed between the PGA and the PGB and disposed on the fin structures of the PLand the PD, a second local interconnection layer disposed between the PGA and the PGB and disposed between the fin structures of the PLand the PD, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.

Static random access memory structure

A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL), a first pull-down transistor (PD), a second (PL), and a second pull-down transistor (PD) on the substrate, and a first pass gate transistor (PGA), a second pass gate transistor (PGB), a third pass gate transistor (PGA) and a fourth pass gate transistor (PGB), wherein the PGA and the PGB comprise an identical first fin structure, the PGA and the PGB comprise an identical second fin structure, a first local interconnection layer disposed between the PGA and the PGB and disposed on the fin structures of the PLand the PD, a second local interconnection layer disposed between the PGA and the PGB and disposed between the fin structures of the PLand the PD

Layout pattern for static random access memory

The present invention proposes a static random-access memory device (SRAM). The static random-access memory device is composed of two P-channel gates of loading transistor, two N-channel gates of driving transistor and two N-channel gates of accessing transistor in a memory cell. A dummy gate is disposed adjacent to the N-channel gate of accessing transistor with a bit line node disposed therebetween, wherein the dummy gate is electrically connected to a ground voltage through a metal layer.

Static random-access memory device

Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.

Dummy gate technology to avoid shorting circuit

A memory device includes a pickup area extending along a first direction. The pickup area includes at least one N-pickup structure, distributing along an N-pickup line extending at the first direction. At least one P-pickup structure distributes by alternating with the N-pickup structure at the first direction and interleaves with the N-pickup structure at a second direction. The second direction is perpendicular to the first direction. Dummy pickup structure distributes along the first direction, opposite to the P-pickup structure with respect to the N-pickup line. Further, a cell area is beside the pickup area. The SRAM cells in the cell area form cell rows extending along the second direction. Each SRAM cell covers one N-type well region along the second direction and two P-type well regions along the second direction to sandwich the N-type well region. The N-pickup/P-pickup structures respectively provide first/second substrate voltage to the N-type/P-type well regions.

Memory device

A semiconductor layout structure includes a substrate comprising a cell edge region and a dummy region abutting thereto, a plurality of dummy contact patterns disposed in the dummy region and arranged along a first direction, and a plurality of dummy gate patterns disposed in the dummy region and arranged along the first direction. The dummy contact patterns and the dummy gate patterns are alternately arranged. Each dummy contact pattern includes an inner dummy contact proximal to the cell edge region and an outer dummy contact distal to the cell edge region, and the inner dummy contact and the outer dummy contact are arranged along a second direction perpendicular to the first direction and spaced apart from each other by a first gap.

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Miaoli County, Taiwan

Li-Ping Huang