Taiwan Semiconductor Manufacturing Comp. Ltd.

Li-Jung Liu

Shu-Hui Wang

Li-Feng Teng

Wei Cheng Wu

Chun-Sheng Liang

Harry-Hak-Lay Chuang

Jyh-Huei Chen

Shih-Hsun Chang

Chih-Pin Tsao

Chia-Wei Soong

Wei-Cheng Wu

Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

Method to embed planar FETs with finFETs

Method to embed planar FETS with FINFETS

A semiconductor device includes a substrate, a first gate structure and a second gate structure, a first gate spacer and a second gate spacer. The first gate spacer includes a first layer, a second layer over the first layer, a third layer over the second layer, a fourth layer over the third layer, and a fifth layer of the fourth layer, in which the first layer, the third layer, and the fifth layer of the first gate spacer are made of a same material. The second gate spacer includes a first layer, a second layer over the first layer, and a third layer over the second layer, in which the first layer and the third layer of the second gate spacer are made of a same material, and in which a lateral width of the first gate spacer is greater than a lateral width of the second gate spacer.

Semiconductor device and method for forming the same

A semiconductor device includes a semiconductor fin, a gate structure, a source epitaxy structure and a drain epitaxy structure. The semiconductor fin extends along a first direction above a substrate. The gate structure extends across the semiconductor fin along a second direction different from the first direction. The gate structure includes a gate dielectric layer wrapping around the semiconductor fin and a chlorine-containing N-work function metal layer wrapping around the gate dielectric layer. The source epitaxy structure and the drain epitaxy structure are on opposite sides of the gate structure, respectively.

Semiconductor device and method of forming the same

A semiconductor device includes a semiconductor fin and a gate structure. The semiconductor fin extends along a first direction above a substrate. The gate structure extends across the semiconductor fin along a second direction substantially perpendicular to the first direction. The gate structure includes a chlorine-containing N-work function metal layer wrapping around the semiconductor fin, and a filling metal over and in contact with the chlorine-containing N-work function metal layer.

A semiconductor device includes a semiconductor substrate, a filling conductor, an N-work function conductor layer and a gate dielectric layer. The filling conductor is over the semiconductor substrate. The N-work function conductor layer wraps around the filling conductor. The N-work function conductor layer comprises chlorine. The gate dielectric layer is between the N-work function conductor layer and the semiconductor.

Semiconductor device with chlorine-containing N-work function conductor and method of forming the same

A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent. An example benefit includes reduction or elimination of diffusion of fluorine contaminants from a gate metal fill layer into its underlying layers and from conductive layers into diffusion barrier layers and silicide layers of source/drain contact structures and consequently, the reduction of the negative impact of these fluorine contaminants on device performance.

Fluorine contamination control in semiconductor manufacturing process

A semiconductor device includes a semiconductor substrate, a plurality of gate spacers and a gate stack. The gate spacers are over the semiconductor substrate. The gate stack is over the semiconductor substrate and between the gate spacers. The gate stack includes a carbon-containing titanium nitride layer and an N-work function conductor layer over the carbon-containing titanium nitride layer.

Growing community of inventors

Kaohsiung, Taiwan

Li-Jung Liu