Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Solar Ltd.

Li-Huan Chu

Pei-Haw Tsao

Tsung-Hsing Lu

Tsui-Mei Chen

Chen-Shien Chen

Jun He

Liang-Chen Lin

Hsu-Hsien Chen

Tsung-Jen Liao

Tsung-Yang Hsieh

Hsin-Hsien Lee

Kuen-Hong Tsai

Sung-Sheng Chiu

Shih-Hsing Lin

Mirng-Ji Lii

Wen-Chin Lee

Yao-Chun Chuang

Kuo-Chin Chang

Lin-June Wu

Hong-Seng Shue

Cheng-Hung Tsai

Cheng-Te Lin

So-Wen Kuo

Yu-Jung Lin

Hsuan-Sheng Yang

Wen-Chung Lee

Chen-Nan Chiu

A semiconductor structure includes a first device and a second device bonded on the first device. The first device has a first sidewall distal to the second device and a second sidewall proximal to the second device. A surface roughness of the second sidewall is larger than a surface roughness of the first sidewall. The second device has a third sidewall proximal to the first device and a fourth sidewall distal to the first device. A surface roughness of the fourth sidewall is larger than a surface roughness of the third sidewall.

Dicing method for stacked semiconductor devices

Generally, the present disclosure provides example embodiments relating to a package that may be attached to a printed circuit board (PCB). In an embodiment, a structure includes a package. The package includes one or more dies and metal pads on an exterior surface of the package. At least some of the metal pads are first solder ball pads. The structure further includes pins, and each of the pins is attached to a respective one of the metal pads.

Package and printed circuit board attachment

An integrated fan-out structure on a semiconductor die, method of making the same and method of testing the semiconductor die are disclosed. The semiconductor die includes a bond pad and a hole formed in the bond pad, a passivation layer formed over a portion of the bond pad, and a protective layer formed over the hole in the bond pad.

Integrated fan-out structures and methods for forming the same

A semiconductor structure includes a first device and a second device bonded on the first device. The first device has a first sidewall distal to the second device and a second sidewall proximal to the second device. A surface roughness of the second sidewall is larger than a surface roughness of the first sidewall.

Stacked semiconductor devices and methods of forming thereof

The current disclosure describes carrier tape systems, which include a cover tape having adhesion areas and non-adhesion areas which are substantially free of adhesive. Methods for supplying semiconductor devices to an apparatus, which in operation, places the semiconductor devices at desired locations are also described. Methods of forming a semiconductor device carrier system are also described.

Carrier tape system and components and methods of use

A non-conductive magnetic shield material is provided for use in magnetic shields of semiconductor packaging. The material is made magnetic by the incorporation of ferromagnetic particles into a polymer matrix, and is made non-conductive by the provision of an insulating coating on the ferromagnetic particles.

Magnetic shielding material with insulator-coated ferromagnetic particles

A package manufacturing process and semiconductor packages are provided. An interposer having a crystal structure is provided. A first die and a second die are bonded on the interposer. The second die is positioned to be spaced apart from the first die with a gap extending direction that is perpendicular to a shortest distance of the gap, and the gap extending direction is not parallel with a crystallographic orientation of the crystal structure of the interposer. A molding compound is formed over the interposer covering the first and second dies. The molding compound and the interposer are cut into packages.

Semiconductor package and manufacturing process thereof

A semiconductor package includes a semiconductor substrate, an interconnect structure disposed over the substrate, a first passivation layer disposed over an interconnect structure, a contact pad disposed over the first passivation layer, a dummy pattern disposed around the contact pad and over the first passivation layer, and a second passivation layer overlaying the dummy pattern and the contact pad.

Semiconductor packages with crack preventing structure

A semiconductor structure includes a first substrate including a first surface and a second surface opposite to the first surface; a first conductive via extended through the first substrate; a second conductive via extended through the first substrate; and a third conductive via extended through the first substrate, wherein the second conductive via is disposed between the first conductive via and the third conductive via, the second conductive via is configured to connect to a signal source, and the first conductive via and the third conductive via are configured to connect to an electrical ground.

Semiconductor structure and manufacturing method thereof

A semiconductor device includes a substrate and at least one bump structure disposed over the substrate. The at least one bump structure includes a pillar formed of a metal having a lower solderability than copper or a copper alloy to a solder alloy disposed over the substrate. A solder alloy is formed directly over and in contact with an upper surface of the metal having the lower solderability than copper or a copper alloy. The pillar has a height of greater than 10 &#x3bc;m.

Growing community of inventors

Hsinchu, Taiwan

Li-Huan Chu