Yangtze Memory Technologies Co., Ltd.

Accelink Technologies Co., Ltd.

Cornell University

Wuhan University

Semiconductor Manufacturing International Corp.

Li Hong Xiao

Jun Chen

Qian Tao

Zhenyu Lu

Zongliang Huo

Jun Liu

Yushi Hu

Yu Ting Zhou

Zhiliang Xia

Zhao Hui Tang

Zhaosong Li

Jifeng Zhu

Xiaowang Dai

Sizhe Li

Haohao Yang

Lan Yao

Jin Wen Dong

Si Ping Hu

Kun Bao

A Man Zheng

Ming Wang

Yue Qiang Pu

Yali Song

Yu Huang

Sha Sha Liu

Jian Xu

Mei Lan Guo

Jian Hua Sun

EnBo Wang

Lijie Qiao

Zi Qun Hua

Qinlian Bu

Meng Wang

Enbo Wang

Qianbing Xu

Bin Hu

Qinxiang Wei

Feng Lu

ZhiWu Tang

LongDong Liu

Chengpeng Fu

Qianggao Hu

Meng Yan

Héctor D Abruña

Liang Xiao

Jin Lyu

Yong Zhang

Jiekui Yu

Qianbin Xu

Weiqing Zhang

Zhi Chen

Zhaoxia Liu

Lin Zhuang

Shasha Liu

Yao Yang

YaLi Song

Hanging Peng

Xiao Tian Cheng

Li Xun Gu

Liyan Huang

Gang Lu

Miao Shen

Provided are a communication station, an optical communication system, a data transmission method, and a storage medium. The communication station is a first station including: a first reconfigurable optical add-drop multiplexing ROADM device, including a first port used to connect a cable in a first direction of a network; a second ROADM device connected to the first ROADM device and including a second port which may be used to connect a cable in a second direction of the network being different from the first direction; an optical protection device connected to each of the first and second ROADM devices and used to control the first station to transmit communication with a second station for a corresponding service in the first direction corresponding to the first ROADM device, or to transmit communication with the second station for a corresponding service in the second direction corresponding to the second ROADM device.

Communication station, optical communication system, data transmission method, and storage medium

A 3D-NAND memory device is provided. The memory device includes a substrate, a bottom select gate (BSG) disposed over the substrate, a plurality of word lines positioned over the BSG with a staircase configuration and a plurality of insulating layers disposed between the substrate, the BSG, and the plurality of word lines. In the disclosed memory device, one or more first dielectric trenches are formed in the BSG and extend in a length direction of the substrate to separate the BSG into a plurality of sub-BSGs. In addition, one or more common source regions are formed over the substrate and extend in the length direction of the substrate. The one or more common source regions further extend through the BSG, the plurality of word lines and the plurality of insulating layers.

3D NAND memory device and method of forming the same

Embodiments of 3D memory devices and fabricating methods thereof are disclosed. The method comprises forming an array device semiconductor structure comprising an alternating conductor/dielectric stack disposed on a semiconductor layer, and an array interconnect layer disposed on the alternating conductor/dielectric stack and including a first interconnect structure. The method further comprises a peripheral device disposed on a substrate, and a peripheral interconnect layer disposed on the peripheral device and including a second interconnect structure and a pad. The pad is electrically connected with the peripheral device through the second interconnect structure. The method further comprises bonding the array interconnect layer to the peripheral interconnect layer, such that the first interconnect structure is joined with the second interconnect structure. The method further comprises forming a pad opening exposing a surface of the pad.

Embedded pad structures of three-dimensional memory devices and fabrication methods thereof

A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Staircase structure for memory device

Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed method comprises forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure. Each one of the plurality of dielectric stacks comprises a plurality of dielectric pairs arranged along a direction perpendicular to a top surface of the substrate. The method further comprises forming a filling structure that surrounds the multiple-stack staircase structure, forming a semiconductor channel extending through the multiple-staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces, and forming a supporting pillar extending through at least one of the multiple-staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.

Multiple-stack three-dimensional memory device and fabrication method thereof

Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.

Method for forming channel hole plug of three-dimensional memory device

Embodiments of methods to form three-dimensional (3D) memory devices include the following operations. First, an initial channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset is formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel is formed by filling the channel hole with a channel-forming structure, the semiconductor channel having a memory layer including a plurality of first memory portions each surrounding a bottom of a respective second layer and a plurality of second memory portions each connecting adjacent first memory portions.

Three-dimensional memory devices and fabrication methods thereof

Aspects of the disclosure provide a method for fabricating semiconductor device. The method includes characterizing an etch process that is used to etch channel holes and dummy channel holes in a stack of alternating sacrificial gate layers and insulating layers upon a substrate of a semiconductor device. The channel holes are in a core region and the dummy channel holes are in a staircase region. The stack of alternating sacrificial gate layers and insulating layers extend from the core region into in the staircase region of a stair-step form. The method further includes determining a first shape for defining the dummy channel holes in a layout based on the characterization of the etch process. The first shape is different from a second shape for defining the channel holes.

Vertical memory devices

A method of forming a structure of 3D NAND memory device, including steps of forming a first stack layer on a substrate, forming a first channel hole extending through the first stack layer, forming a block layer on a surface of the first stack layer and the first channel hole, forming a sacrificial layer in the first channel hole, forming a second stack layer on the first stack layer and the sacrificial layer, performing a first etch process to form a second channel hole extending through the second stack layer and at least partially overlapping the first channel hole and to remove the sacrificial layer in the first channel hole, removing the block layer exposed from the second channel hole, and forming a function layer on a surface of the first channel hole and the second channel hole.

Structure of 3D NAND memory device and method of forming the same

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. a memory stack including a plurality of interleaved gate conductive layers and gate-to-gate dielectric layers above a substrate is formed. Each of the gate-to-gate dielectric layers includes a silicon nitride layer. A NAND memory string extending vertically through the interleaved gate conductive layers and gate-to-gate dielectric layers of the memory stack is formed. A slit structure extending vertically through the interleaved gate conductive layers and gate-to-gate dielectric layers of the memory stack is formed.

Memory stacks having silicon nitride gate-to-gate dielectric layers and methods for forming the same

A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming an alternating layer stack on a substrate; forming a plurality of channel holes in the alternating layer stack, each penetrating vertically through the alternating layer stack; forming a functional layer including a storage layer on a sidewall of each channel hole, wherein the storage layer has an uneven surface; forming a channel layer to cover the functional layer in each channel hole; and forming a filling structure to cover the channel layer and fill each channel hole.

Three-dimensional memory devices and fabricating methods thereof

In a method for manufacturing a memory device, a plurality of first insulating layers and a bottom select gate (BSG) layer are formed over a substrate, where the first insulating layers are disposed between the substrate and the BSG layer. One or more first dielectric trenches are formed to pass through the BSG layer and the first insulating layers, and extend in a length direction of the substrate. A plurality of word line layers and a plurality of second insulating layers are formed over the BSG layer, where the second insulating layers are disposed between the BSG layer and the word line layers. One or more common source regions are formed over the substrate to extend in the length direction of the substrate, and further extend through the BSG layer, the first insulating layers, the word line layers, and the second insulating layers.

A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming a plurality of hybrid shallow trench isolation structures in a substrate, each hybrid shallow trench isolation structure comprising a dielectric sublayer and a conductive sublayer, both of which are embedded in the substrate; forming an alternating dielectric stack on the substrate; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction to expose a row of hybrid shallow trench isolation structures; forming a plurality of array common source contacts in the slit, each array common source contact being in electric contact with a corresponding hybrid shallow trench isolation structure.

Embodiments of three-dimensional (3D) memory devices having a shielding layer and methods for forming the 3D memory devices are disclosed. In an example, a method for forming a 3D memory device is disclosed. A peripheral device is formed on a first substrate. A first interconnect layer including first interconnect structures are formed above the peripheral device on the first substrate. A shielding layer including a conduction region is formed above the first interconnect layer on the first substrate. The conduction region of the shielding layer covers substantially an area of the first interconnect structures in the first interconnect layer. An alternating conductor/dielectric stack and memory strings each extending vertically through the alternating conductor/dielectric stack are formed on a second substrate. A second interconnect layer including second interconnect structures is formed above the plurality of memory strings on the second substrate. The first substrate and the second substrate are bonded in a face-to-face manner, such that the shielding layer is between the first interconnect layer and the second interconnect layer.

Three-dimensional memory device having a shielding layer and method for forming the same

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Hubei, China

Li Hong Xiao