Chinese Academy of Sciences

Shanghai Huali Microelectronics Corporation

Li He

Xiaoming Xie

Haomin Wang

Hong Xie

Lingxiu Chen

Huishan Wang

Yi Bin Wang

Lei Li

Liyuan Liu

Fulong Qiao

Mianheng Jiang

Guanqun Huang

Shujie Tang

Xiujun Wang

Xiaohua Ju

Daoli Zhang

The disclosure provides a method for manufacturing shallow trench isolations, providing a substrate comprising a storage cell area and a peripheral area of a storage device; etching the upper part of the substrate of the storage cell area using a first etching process to form a first shallow trench, and filling the first shallow trench with silicon oxide using a first deposition process; and etching the upper part of the substrate of the peripheral area using a second etching process to form a second shallow trench, and filling the second shallow trench with silicon oxide using a second deposition process; wherein the depth and characteristic dimension of the first shallow trench are smaller than the depth and characteristic dimension of the second shallow trench. The disclosure can avoid the silicon dislocation defect of the peripheral area and ensure the device shape and characteristic dimension of the storage cell area.

Method for manufacturing shallow trench isolations

The present invention provides a method for optimizing a critical dimension for double patterning for NAND flash, forming a core oxide layer on amorphous silicon layer on substrate; densifying the core oxide layer and etching it to form a core pattern; measuring CD values of the bottom and top of the core pattern; providing etching rates of a non-densified core oxide layer and a densified core oxide layer under the same etching condition; calculating the thickness of the core oxide layer required to be densified according to the CD values of the bottom and top of the core pattern and the etching rates to determine the densifying time. The present invention precisely controls the morphology and CD, and obtains a double-patterned target pattern with consistent CD sizes of a top and a bottom and a consistent bottom height, so as to improve a product yield.

Method for optimizing a critical dimension for double patterning for NAND flash

A method for adjusting and controlling a boundary of graphene, comprising: providing an insulating substrate and placing the insulating substrate in a growth chamber; and feeding first reaction gas into the growth chamber, the first reaction gas at least comprising carbon source gas, and controlling a flow rate of the first reaction gas to forming a graphene structure having a first boundary shape on a surface of the insulating substrate through controlling a flow rate of the first reaction gas. The present invention realizes the controllability of the boundary of the graphene by adjusting the ratio of the carbon source gas to catalytic gas in the growth process of graphene on the surface of the substrate; the present invention can enable graphene to sequentially continuously grow by changing growth conditions on the basis of already formed graphene, so as to change the original boundary shape of the graphene.

Method for adjusting and controlling boundary of graphene

A preparation method of a graphene nanoribbon on h-BN, comprising: 1) forming a h-BN groove template with a nano ribbon-shaped groove structure on the h-BN by adopting a metal catalysis etching method; 2) growing a graphene nanoribbon in the h-BN groove template by adopting a chemical vapor deposition method. In the present invention, a CVD method is adopted to directly prepare a morphology controllable graphene nanoribbon on the h-BN, which helps to solve the long-term critical problem that the graphene is difficult to nucleate and grow on an insulating substrate, and to avoid the series of problems introduced by the complicated processes of the transferring of the graphene and the subsequent clipping manufacturing for a nanoribbon and the like.

Preparation method of graphene nanoribbon on h-BN

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Shanghai, China

Li He