Taiwan Semiconductor Manufacturing Comp. Ltd.

National Yang Ming Chiao Tung University

Wistron Neweb Corporation

Other

Li-Han Hsu

Wei-Cheng Wu

Cheng-Hsien Hsieh

Hsien-Wei Chen

Der-Chyang Yeh

Chen-Hua Douglas Yu

Chi-Hsi Wu

Tsung-Shu Lin

Chien-Chia Chiu

Shin-Puu Jeng

Shang-Yun Hou

Meng-Tsan Lee

Wei-Chih Lai

Wen-Chih Chiou

Ku-Feng Yang

Yung-Chi Lin

Tsung-Yu Chen

Yi-Chieh Lin

Sao-Ling Chiu

Yi-Hsiu Chen

Edward Yi Chang

Chen-Hua Lin

Lan-Chun Yang

Chun-Hung Huang

Jun-Lin Yeh

Yu-Chen Hsu

Lai Wei Chih

Ruey-Bing Hwang

Chien-Fu Tseng

Che-Yu Yeh

Pei-Ching Kuo

Edward-yi Chang

Chee-Way Oh

Chin-te Wang

Hsien-Pin Hu

Tzu-Yu Wang

Yan-Fu Lin

Tzu-Shiun Sheu

Chin-Te Wang

Meng-Han Lee

A communication apparatus and a bracket device thereof are provided. The bracket device includes a base, a rotary shaft, a connecting member, and an elastic member. The base includes a bottom portion, a connecting portion, and a base engaging portion. The rotary shaft is rotatably disposed in the connecting portion and includes a base wall and a connecting section. The connecting member connects to the rotary shaft. The elastic member includes a body and an elastic member engaging portion. The body connects to the base wall of the rotary shaft, and the elastic member engaging portion is positioned at the body. In an engagement state, the elastic member engaging portion is engaged to the base engaging portion.

Communication apparatus and bracket device thereof

A method of forming an integrated circuit package includes following operations. A padding layer is formed on a portion of a carrier. A first semiconductor die is placed on the padding layer and a second semiconductor die is placed on the carrier. The first semiconductor die and the second semiconductor die are encapsulated with a first encapsulation layer. A first redistribution layer structure is formed over the first semiconductor die, the second semiconductor die and the first encapsulation layer. A third semiconductor die is placed on the first redistribution layer structure. The third semiconductor die is encapsulated with a second encapsulation layer. A second redistribution layer structure is formed over the third semiconductor die and the second encapsulation layer. The carrier is debonded. The padding layer is removed, and therefore, a recess is formed in the first encapsulation layer.

Method of forming an integrated circuit package having a padding layer on a carrier

A semiconductor device including a circuit substrate, a chip package, and a stiffener ring is provided. The chip package is disposed on and electrically connected to the circuit substrate, the chip package includes a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides. The stiffener ring is disposed on the circuit substrate, the stiffener ring includes first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides. The first stiffener portions are connected to the second stiffener portions, and the second stiffener portions is mechanically weaker than the first stiffener portions. A semiconductor device including stiffener lids is also provided.

Semiconductor device

A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

Semiconductor package and manufacturing method thereof

A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.

Stacked via structure disposed on a conductive pillar of a semiconductor die

A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

Semiconductor package with redistribution structure and manufacturing method thereof

An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.

Semiconductor package and method of forming the same

An orientation-adjustment mechanism is provided, which is adapted to be affixed to a mounting surface. The orientation-adjustment mechanism includes a base, a rod, a joint unit, and a mounted member. The base is adapted to be affixed to the mounting surface. The rod includes a first section and a second section. The first section of the rod pivots on the base. The joint unit is disposed on the second section of the rod. The joint unit includes a plurality of joint-positioning portions. The joint-positioning portions include a first joint-positioning portion and a second joint-positioning portion. The mounted member is connected to the joint unit and is adapted to be rotated relative to the joint unit. The mounted member includes a member housing. The member housing includes at least one member-positioning portion.

Orientation-adjustment mechanism

A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.

Opening in the pad for bonding integrated passive device in InFO package

A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate.

An embodiment package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.

Redistribution layers in semiconductor packages and methods of forming same

Semiconductor package including shielding plate in redistribution structure, semiconductor package including conductive via in redistribution structure, and manufacturing method thereof

Growing community of inventors

Hsinchu, Taiwan

Li-Han Hsu