Mosel Vitelic Corporation

Promos Technologies, Inc

Vitelic Corporation

Mosel Vitalic Corporation

Li-Chun Li

Michael A Murray

Lawrence C Liu

Hsing Ti Tuan

Chung-Cheng Wu

Huoy-Jong Wu

Saysamone Pittikoun

Wen-Wei Lo

Vei-Han Chan

Jongmin Park

Thomas Tong-Long Chang

Pochung Young

Chung Wai Leung

Steve Eaton

Jinyong Chung

Sharlin Fang

Lynne Watters

Lynne Hannah

Jin Seung Song

Youngweon Kim

Jin Seung Son

Nonvolatile memory cells () are connected to a bitline (BL). The bitline is also connected to a source/drain region () of a transistor (), a Y multiplexer transistor for example. This source/drain region is exposed to a higher voltage, and hence is made to have a higher junction breakdown voltage, than the other source/drain region () of the same transistor. A nonvolatile memory has a plurality of memory arrays (), a global decoder () and secondary decoders (). The selection signals provided by the global decoder to the secondary decoders for selecting the control gate lines () and the source lines () are carried by lines () running in the row direction. These signals are low voltage signals (between 0V and Vcc). The super high voltages are carried by lines () extending in the column direction to reduce noise injection into the control gate lines, source lines, and wordlines (), and to reduce the parasitic capacitance associated with the super high voltage lines. An integrated circuit has at least two memory arrays () with control gate lines (), source lines (), and wordlines (). A global decoder () and secondary decoders () select the control gate lines and the source lines. Each secondary decoder is located in an area spaced from the arrays. The control gate line and source line decoding circuits in each secondary decoder share a common area to reduce the memory size. Other features are also provided.

Nonvolatile memories with asymmetric transistors, nonvolatile memories with high voltage lines extending in the column direction, and nonvolatile memories with decoding circuits sharing a common area

In some embodiments, of the present invention, data are written to a plurality of nonvolatile memory cells (Q, Q) as follows. A data writing signal is supplied to one of the memory cells (Q) but not to both of the memory cells. Then data writing signals are supplied to both of the memory cells simultaneously.

Writing data to nonvolatile memory

A memory such as a flash EPROM contains writing circuitry (and) that adjusts how much current or/and voltage is provided to a writing conductor () connected to the memory cells () of a cell group for simultaneously writing the bits of a bit group such as a word or byte into the cells of that cell group as a function of how many of those bits are in one of a pair of opposite logic states.

Electronic memory, such as flash EPROM, with bitwise-adjusted writing current or/and voltage

Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N&plus; contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N&plus; contact region.

Method for fabricating an integrated circuit with a transistor electrode

A nonvolatile memory array can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells of the array in parallel.

Nonvolatile memory structures and fabrication methods

A memory performs a hidden refresh only at the end of a read operation or when the memory is disabled but is supposed to retain data in the disabled state. When the memory is in the enabled state, the refresh is not performed at the end of any operation other than read. This is done to ensure that execution of any memory access command will not be delayed by a refresh as long as the user follows certain timing rules. Other embodiments arc also provided.

Memory refresh methods and circuits

In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

Nonvolatile memory structures and access methods

In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask ( ) is used to remove the select gate layer from over the source lines ( ), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order-to block the channels stop implant from an N&plus; contact region used for DNW biasing. In DRAMS and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N&plus; contact region.

In a burst operation, a counter receives one or more bits of a starting column address. The count signal generated by the counter is provided to column decoders. The column decoders select two columns in response to a single value of the count signal. The two columns can be at non-consecutive column addresses. Alternatively, the two columns can be at consecutive column addresses starting at an odd column address boundary. Data are transferred between the two columns and a buffer in parallel. Data are transferred between the buffer and a data terminal serially. Some embodiments are suitable for burst operations defined by standards for synchronous dynamic random access memories.

Burst operations in memories

In a burst operation, a counter (,) receives one or more bits of a starting column address. The count signal (A&lsqb;,&rsqb;) generated by the counter is provided to an address adder (,). The address adder generates column address bits (B&lsqb;,&rsqb;) for a column to be selected in the burst operation. The Y-decoder circuitry (,) selects an even column and an odd column in parallel. The count address bits (A&lsqb;,&rsqb;) are used as address bits for the even column, and the address bits (B&lsqb;,&rsqb;) generated by the address adder are used as address bits for the odd column, or vice versa. The even and odd columns can be at non-consecutive column addresses, or they can be at consecutive column addresses starting at an odd column address boundary. Some embodiments are suitable for burst operations defined by standards for synchronous dynamic random access memories. Some embodiments are suitable for double data rate memories.

Memory burst operations in which address count bits are used as column address bits for one, but not both, of the odd and even columns selected in parallel.

In accordance with the present invention, a circuit provides a bias voltage V,which is substantially insensitive to variations of a power supply voltage powering the circuit. The circuit includes a detector circuit for generating a signal from the power supply voltage and the bias voltage V,wherein the signal is substantially insensitive to variations in the power supply voltage while being responsive to the bias voltage V,The circuit further includes a voltage generator circuit for generating the bias voltage V,wherein the voltage generator is responsive to the signal such that the detector circuit and the voltage generator maintain the bias voltage V,at a substantially constant value over power supply voltage variations. The detector circuit also includes a circuit for allowing bias voltage V,to get arbitrarily close to the ground voltage but not allowing the bias voltage V,to become positive.

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Los Gatos, CA, United States of America

Li-Chun Li