Advanced Micro Devices Corporation

Other

Lewis N Shen

Wenge Yang

Robin W Cheung

Richard J Huang

Marina V Plat

Mark S Chang

Ramkumar Subramanian

Suzette Keefe Pangrle

Robert B Ogle

Kathleen R Early

Maria Chow Chan

Pankaj Dixit

Mohammad Farnaam

Jack Sliwa

Sheshadri Ramaswami

Fei Wang

Mark T Ramsbey

Angela Tai Hui

Tuan Duc Pham

Jeffrey Allan Shields

Hsingya Arthur Wang

James Juen Hsu

Anne E Sanderfer

Zahra Hadjizadeh-Amini

Tommy C Hsiao

A method is provided for manufacturing a semiconductor device on a semiconductor substrate using a dielectric as a bottom anti-reflective coating for formation of a photoresist contact opening which is used to enlarge the Final Inspection Critical Dimension (FICD) of the conductive contact. A high selectivity etch is used to form a tapered contact.

Method for forming SAC using a dielectric as a BARC and FICD enlarger

An improved method of making a flash memory cell including a substrate having a floating gate of a first thickness includes depositing an insulator on the substrate and over the floating gate. The insulator is preferably a high quality oxide. A portion of the insulator not covering the floating gate has a second thickness which is greater than the first thickness of the floating gate. The method further includes polishing the insulator until the second thickness is substantially equal to the first thickness. Polishing results in a planar floating gate and insulator layer. The method further includes sequentially depositing a dielectric layer and a control gate layer on the planar floating gate and insulator layer and then etching these layers to complete the stacked gate structure of the memory cell.

Method of making a memory cell with polished insulator layer

A thin barrier layer of undoped silicon is formed on an ARC to prevent resist poisoning and footing. The silicon layer can be removed with improved yield and high selectivity with respect to the underlying gate dielectric layer, thereby avoiding degradation of the gate dielectric layer. Embodiments include forming a silicon oxynitride ARC on a polycrystalline silicon layer overlying a silicon oxide layer, depositing a thin undoped polycrystalline or amorphous silicon barrier layer on the ARC, forming a photoresist mask on the barrier layer, etching to form a gate electrode on a gate oxide layer and removing the photoresist mask. The undoped polycrystalline or amorphous silicon barrier layer is then removed employing conventional wet or dry etching techniques with high etch selectivity to the underlying gate oxide layer, thereby avoiding degradation of the gate oxide layer.

Silicon barrier layer to prevent resist poisoning

The high density plasma metal etch rate of a conductive material within a dense array of conductive lines is increased to greater than the etch rate of the conductive material in a bordering open field by controlling the source power and the bottom power in a plasma chamber, thereby reducing overetching, resist loss, and oxide loss in the open field, and facilitating planarization.

Method of high density plasma metal etching

The use of chlorine and oxygen chemistry in a polysilicon etch environment provides a process to etch a plurality of silicon-based layers on a semiconductor substrate to an underlying oxide layer in a single step. The process is useful in the formation of gate structures wherein high selectivity to the underlying oxide layer thereby affords higher processing control over the formed gate structure.

Semiconductor devices with reduced control gate dimensions

A resist mask pattern having a reduced thickness is formed overlying on a silicon oxynitride film during formation of a memory gate. The resist mask pattern has a resist thickness (3000 to 4000 Angstroms) sufficient to withstand removal during etching of the silicon oxynitride film. The silicon oxynitride film, having a thickness of about 800 to 1500 Angstroms, is etched based on the resist mask pattern and then used as a mask pattern to etch the polysilicon gate layer underlying the silicon oxynitride layer, to expose a portion of an isolation region aligned relative to the resist mask pattern. The portion of the resist mask remaining after etching, in combination with the etched silicon oxynitride film, have a sufficient overall thickness to serve as a channel implant mask. Use of the resist mask pattern having the reduced thickness improves yield by minimizing the occurrence of misregistration, and enables reliable formation of spaces in the mask pattern having widths of less than 0.25 microns using conventional deep ultraviolet (DUV) photolithography techniques.

Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride

A memory gate stack in a high density memory core has spaces on the order of less than 0.25 microns using conventional deep ultraviolet (DUV) lithography techniques by depositing a layer of silicon oxynitride over a plurality of layers, and a thin resist layer overlying on the silicon oxynitride layer. The resist layer has a thickness sufficient to withstand removal during etching of the silicon oxynitride layer, for example about 3,000 Angstroms to about 4,000 Angstroms. The silicon oxynitride layer has a sacrificial portion having a thickness at least about 500 Angstroms, and a stop-layer thickness, used for spacer formation following etching of the memory gate, of at least 1,000 Angstroms. The use of silicon oxynitride as an antireflective coating layer in combination with the thin resist optimizes the resolution of DUV lithography, enabling formation of spacers having widths less than about 0.24 microns. In addition, the sacrificial layer of the silicon oxynitride layer enables self-aligned etching of the plurality of layers to form the memory gate stack, while maintaining sufficient thickness for spacer formation.

Method for etching memory gate stack using thin resist layer

Memory gate stacks having widths of about 0.18 microns to 0.15 microns are formed by trimming a resist mask pattern, having line widths of about 0.25 microns, to a width of about 0.20 microns. An antireflective coating layer such as silicon oxynitride underlying the resist pattern is then etched to form etched silicon oxynitride pattern lines having widths of about 0.18 to 0.15 microns. The etched silicon oxynitride layer is then used for self-aligned etching of underlying layers to form the memory gate stack. Hence, a memory gate can be formed that has a width substantially less than the current photolithography limit during formation of the resist mask pattern.

Method for trimming a photoresist pattern line for memory gate etching

A method is provided for manufacturing a semiconductor with fewer steps and minimized variation in the etching process by using SiON as a bottom antireflective (BARC) layer and hard mask in conjunction with a thin photoresist layer. In one embodiment, an etch-stop layer is deposited on a semiconductor substrate, a dielectric layer is deposited on top of the etch-stop layer, a BARC is deposited on top of the dielectric layer, and a photoresist layer with a thickness less than the thickness of the BARC is then deposited on top of the BARC. The photoresist is then patterned, photolithographically processed, and developed. The BARC is then etched away in the pattern developed on the photoresist and to photoresist is then removed. The BARC is then used as a mask for the etching of the dielectric layer and is subsequently removed in the process of etchings the dielectric and etch-stop layers without the benefit of a separate BARC-removal step.

Semiconductor manufacturing method using a dielectric photomask

A thermally grown oxide buffer layer is formed on a silicon layer prior to depositing an ARC thereon, thereby preventing damage to the silicon layer during ARC removal. Embodiments include thermally growing a silicon oxide buffer layer on an amorphous or polycrystalline silicon layer by thermal oxidation at a temperature of about 800&deg; C. to about 900&deg; C. in an atmosphere comprising oxygen or steam. A silicon oxynitride or silicon-rich silicon nitride ARC is then formed on the thermally grown protective silicon oxide buffer layer and a photoresist layer is formed on the ARC. The photoresist layer is patterned to form a mask and the underlying silicon layer etched to form a conductive feature, e.g., gate electrode. The photoresist mask is then removed and the ARC is stripped with hot phosphoric acid or by dry etching, while the thermally grown silicon oxide buffer layer protects the underlying silicon layer from damage.

Thermally grown protective oxide buffer layer for ARC removal

In the manufacture of sub-0.35 micron semiconductors using deep ultraviolet lithography, a bilayer of silicon dioxide on top of silicon oxynitride is used as bottom anti-reflective coating and an etch hard mask for photolithographic resist. Since the silicon dioxide is optically transparent at the deep ultraviolet wavelengths being used (248 nm), its thickness in combination with a preselected reflective silicon oxynitride thickness satisfies the zero reflectivity goal and, at the same time, is adequately thick to serve as a hard mask for self-aligned etch and self-aligned-source etch.

Bilayer anti-reflective coating and etch hard mask

An oxide buffer layer is formed between an underlying silicon layer and overlying ARC to prevent damage to the silicon layer when removing the ARC. Embodiments include depositing a silicon oxide buffer layer on an amorphous or polycrystalline silicon layer by PCVD, LPCVD or high temperature CVD, forming a SiON or Si-rich SiN ARC on the silicon oxide buffer layer, forming a photoresist mask on the ARC, patterning the underlying silicon layer to form a conductive line or gate electrode, stripping the photoresist mask and then stripping the ARC with hot phosphoric acid while the silicon oxide buffer layer protects the underlying silicon feature from pitting.

Protective oxide buffer layer for ARC removal

A hard resist layer is formed on and/or within a deep-UV configured resist mask prior to patterning a semiconductor device feature. The hard resist layer reduces the amount of polymer residue generated during the patterning process, which can effect the resulting profile of the device feature. The hard resist mask is formed by either ion implantation or plasma treatments. Due to the formation of the hard resist layer, the thickness of the resist mask can be reduced, thereby increasing the resolution capabilities of the resist mask.

Methods for treating a deep-UV resist mask prior to gate formation etch to improve gate profile

In the manufacture of sub 0.35 micron semiconductors using deep ultraviolet lithography, a bilayer of silicon dioxide on top of silicon oxynitride is used as bottom anti-reflective coating and an etch hard mask for photolithographic resist. Since the silicon dioxide is optically transparent at the deep ultraviolet wavelengths being used (248 nm), its thickness in combination with a preselected reflective silicon oxynitride thickness satisfies the zero reflectivity goal and, at the same time, is adequately thick to serve as a hard mask for self-aligned etch and self-aligned-source etch.

A hard resist layer is formed on and/or within a deep-UV configured resist mask prior to patterning a semiconductor device feature. The hard resist layer reduces the amount of polymer residue generated during the patterning process, which can affect the resulting profile of the device feature. The hard resist mask is formed by subjecting the resist mask to a rapid thermal anneal (RTA) type of process. Because of the hard resist layer, the thickness of the resist mask can also be reduced, thereby increasing the resolution capabilities of the resist mask.

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Cupertino, CA, United States of America

Lewis N Shen