Spin Memory, Inc.

Integrated Silicon Solution, (cayman) Inc.

Spin Transfer Technologies, Inc.

Lester Crudele

Benjamin S Louie

Neal Berger

Mourad El-Baraji

Daniel L Hillman

Mourad El Baraji

Barry Hoberman

Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a memory system comprises: an array of addressable memory cells, wherein the addressable memory cells of the array comprise magnetic random access memory (MRAM) cells and wherein further the array is organized into a plurality of banks; an engine configured to control access to the addressable memory cells organized into the plurality of banks; and a pipeline configured to perform access control and communication operations between the engine and the array of addressable memory cells. At least a portion of operations associated with accessing at least a portion of one of the plurality of memory banks via the pipeline are performed substantially concurrently or in parallel with at least a portion of operations associated with accessing at least another portion of one of the plurality of memory banks via the pipeline.

MRAM access coordination systems and methods via pipeline in parallel

A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells and a pipeline configured to process write operations of a first plurality of data words addressed to the memory bank. The memory also comprises a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the second plurality of data words are a subset of the first plurality of data words, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank, and wherein a write verification operation associated with a data word of the second plurality of data words is performed a predetermined period of time after the data word is written into the memory.

Circuit engine for managing memory meta-stability

MRAM access coordination systems and methods with a plurality of pipelines

A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. Also, the cache memory is divided into a plurality of segments, wherein each segment of the cache memory is direct mapped to a corresponding segment of the memory bank, wherein an address of each of the second plurality of data words is mapped to a corresponding segment in the cache memory, and wherein data words from a particular segment of the memory bank only get stored in a corresponding direct mapped segment of the cache memory.

Error cache segmentation for power reduction

A method of writing data utilizes a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method also comprises writing a second plurality of data words into an error buffer, wherein the second plurality of data words comprises data words that are awaiting write verification. Additionally, the method comprises searching for at least one data word that is awaiting write verification in the error buffer, wherein verify operations associated with the at least one data word occur in a same row as the write operation. Finally, the method comprises determining if an address associated with any of the at least one data word is proximal to an address for the write operation and preventing a verify operation associated with the at least one data word from occurring in a same cycle as the write operation.

MRAM noise mitigation for write operations with simultaneous background operations

A method of writing data into a memory device discloses utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a second plurality of data words into an error buffer, wherein the second plurality of data words comprises data words that are awaiting write verification associated with the memory bank. The method further comprises searching for a data word that is awaiting write verification in the error buffer, wherein the verify operation occurs in a same row as the write operation. The method also comprises determining if an address of the data word is proximal to an address for the write operation and responsive to a positive determination, delaying a start of the verify operation so that a rising edge of the verify operation occurs a predetermined delay after a rising edge of the write operation.

MRAM noise mitigation for background operations by delaying verify timing

An memory device comprising an array of memory cells wherein each memory cell includes a respective magnetic random access memory (MRAM) element, and a respective gating transistor. A plurality of bit lines are routed parallel to each other, wherein each bit line is associated with a respective memory cell of the array of memory cells. A common word line is coupled to gates of gating transistors of the array of memory cells. A common source line is coupled to sources of the gating transistors, wherein the common source line is routed perpendicular to the plurality of bit lines within the array of memory cells. A first circuit provides a first voltage on an addressed bit line of the plurality of bit lines during a write cycle, wherein the addressed bit line corresponds to an addressed memory cell. A second circuit provides a second voltage on remainder bits lines of the plurality of bit lines, wherein the second voltage is operable to be applied to the common source line, via the remainder bit lines, during the write cycle.

Memory array with horizontal source line and a virtual source line

A method for correcting bit defects in an STT-MRAM memory is disclosed. The method includes reading a codeword in the STT-MRAM memory, wherein the STT-MRAM memory includes a plurality of codewords, wherein each codeword includes a plurality of redundant bits. Further, the method includes mapping defective bits in the codeword to redundant bits of the plurality of redundant bits based on a mapping scheme, wherein the mapping scheme is operable to determine a manner in which the defective bits in the codeword are to be mapped to the redundant bits. Finally, the method includes replacing the defective bits in the codeword with corresponding mapped redundant bits.

Over-voltage write operation of tunnel magnet-resistance ('TMR') memory device and correcting failure bits therefrom by using on-the-fly bit failure detection and bit redundancy remapping techniques

A memory device for storing data is disclosed. The memory device comprises a plurality of memory banks, wherein each memory bank comprises a plurality of addressable memory cells. The memory device also comprises a plurality of pipelines each comprising a plurality of pipestages, wherein each pipeline is associated with a respective one of the plurality of memory banks. Further, the device comprises a plurality of cache memories, wherein each cache memory is associated with a respective one of the plurality of memory banks and a respective one of the plurality of pipelines, and wherein each cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with a given segment of an associated memory bank or is to be re-written into a given segment of said associated memory bank.

Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register

A memory device includes a write port, a read port, source lines, bit lines, and word lines orthogonal to the bit lines. The memory device also includes memory cells that can be arrayed in columns that are parallel to the bit lines and in rows that are orthogonal to the bit lines. The memory cells are configured so that a write by the write port to a first memory cell in a column associated with (e.g., parallel to) a first bit line and a read by the read port of a second memory cell in a column associated with (e.g., parallel to) a second, different bit line can be performed during overlapping time periods (e.g., at a same time or during a same clock cycle).

Multi-port random access memory

A method for correcting bit defects in an STT-MRAM memory is disclosed. The method comprises executing a read before write operation in the STT-MRAM memory, wherein the STT-MRAM memory comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. The read before write operation comprises reading a codeword and mapping defective bits in the codeword. Further, the method comprises replacing the defective bits in the codeword with a corresponding redundant bit and executing a write operation with corresponding redundant bits in place of the defective bits.

On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defects

A method for correcting bit defects in a memory array is disclosed. The method comprises determining, during a characterization stage, a resistance distribution for the memory array by classifying a state of each bit-cell in the memory array, wherein the memory array comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. Further, the method comprises determining bit-cells in the resistance distribution that are ambiguous, wherein ambiguous bit-cells have ambiguous resistances between being high or low bits. Subsequently, the method comprises forcing the ambiguous bit-cells to short circuits and replacing each short-circuited ambiguous bit-cell with a corresponding redundant bit from an associated codeword.

Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct them

A method for correcting bit defects in a memory array is disclosed. The method comprises determining a margin area associated with a resistance distribution for the memory array, wherein the resistance distribution comprises a distribution of bit-cell resistances for all bits comprising the memory array, wherein the margin area is a bandwidth of bit-cell resistances centered around a reference point associated with a sense amplifier, wherein the bit-cell resistances of memory bit-cells associated with the margin area are ambiguous. The method further comprises forcing the bit-cell resistances of memory bit-cells associated with the margin area to short circuits. Finally, the method comprises replacing each short-circuited memory bit-cell with a corresponding redundant bit in the codeword associated with the short-circuited memory bit-cell.

Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiers

A memory device for storing data is disclosed. The memory device comprises a memory bank comprising a memory array of addressable memory cells and a pipeline configured to process read and write operations addressed to the memory bank. Further, the memory device comprises an x decoder circuit coupled to the memory array for decoding an x portion of a memory address for the memory array and a y multiplexer circuit coupled to the memory array and operable to simultaneously multiplex across the memory array based on two y portions of memory addresses and, based thereon with the x portion, for simultaneously writing a value and reading a value associated with two separate memory cells of the memory array, wherein the x decoder and the y multiplexer are implemented to provide a read port and a write port which are operable to simultaneously operate with respect to the memory array.

Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank

A memory pipeline for performing a write operation in a memory device is disclosed. The memory pipeline comprises an input register operable to receive a first data word and an associated address to be written into a memory bank. The memory pipeline also comprises a pre-read register of the first pipe-stage coupled to the input register and operable to receive the first data word and the associated address from the input register and further operable to pre-read a second data word stored in the memory bank at the associated address. Finally, the memory pipeline comprises a write register of the second pipe-stage operable to receive the first data word, the associated address and mask bits from the pre-read register, wherein the write register is further operable to use information from the mask bits to write the first data word into the memory bank by changing those bits in the first data word that differ from the second data word.

Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers

Growing community of inventors

Tomball, TX, United States of America

Lester Crudele