Tegal Corporation

Silicon Valley Bank

Oem Group, LLC

Leslie G Jerde

Stephen P DeOrnellas

Alferd Cofer

Kurt A Olson

Robert C Vail

Satish D Athavale

Paritosh Rajora

Steven Marks

John A Meyer

Alfred Cofer

A reactor for processing semiconductor wafers with electrodes and other surfaces that can be one of heated, textured and/or pre-coated in order to facilitate adherence of materials deposited thereon, and eliminate the disadvantages resulting from the spaulding, flaking and/or delaminating of such materials which can interfere with semiconductor wafer processing.

Reactor with heated and textured electrodes and surfaces

A plasma etch reactorincludes a upper electrode, a lower electrode, a peripheral ring electrodedisposed therebetween. The upper electrodeis grounded, the peripheral electrodeis powered by a high frequency AC power supply, while the lower electrodeis powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamberis configured with a solid sourceof gaseous species and a protruding baffle. A nozzleprovides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer. The configuration of the plasma etch reactorenhances the range of densities for the plasma in the reactor, which range can be selected by adjusting more of the power supplies

Plasma etch reactor and method

A method for containing the critical dimension growth of the feature on a semiconductor substrate includes placing a substrate with a hard mask comprised of a reactive metal or an oxidized reactive metal in a chamber and etching the wafer. The method further includes using a hard mask which has a low sputter yield and a low reactivity to the etch chemistry of the process.

Method for using a hard mask for critical dimension growth containment

A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor and controlling the temperature of the wafer by controlling the pressure of the gas contacting the backside of the wafer and/or providing a heat source such as for example in the chuck or electrode associated with the wafer in order to heat the wafer

Method for minimizing the critical dimension growth of a feature on a semiconductor wafer

A plasma etch reactor includes a upper electrode , a lower electrode , a peripheral ring electrode disposed therebetween. The upper electrode is grounded, the peripheral electrode is powered by a high frequency AC power supply, while the lower electrode is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber is configured with a solid source of gaseous species and a protruding baffle . A nozzle provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer . The configuration of the plasma etch reactor enhances the range of densities for the plasma in the reactor , which range can be selected by adjusting more of the power supplies

Method and apparatus for etching a silicide stack including etching the silicide layer at a temperature elevated from that used to etch the rest of the layers in order to accomplish anisotropic etch.

Cobalt silicide etch process and apparatus

A method and apparatus for minimizing or eliminating arcing or dielectric breakdown across a wafer during a semiconductor wafer processing step includes controlling the voltage across the wafer so that arcing and/or dielectric breakdown does not occur. Using an electrostatic clamp of the invention and by controlling the specific clamp voltage to within a suitable range of values, the voltage across a wafer is kept below a threshold and thus, arcing and/or dielectric breakdown is reduced or eliminated.

Method and apparatus for minimizing semiconductor wafer arcing during semiconductor wafer processing

Plasma etch reactor having a plurality of magnets

A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor 20 and controlling the temperature of the wafer 26 by controlling the pressure of the gas contacting the backside of the wafer 26 and/or providing a heat source 56 such as for example in the chuck 46 or electrode 28 associated with the wafer 26 in order to heat the wafer 26.

Growing community of inventors

Novato, CA, United States of America

Leslie G Jerde