Sanechips Technology Co., Ltd.

Leqi Li

Yelei Xie

Jian Pang

Tuobei Sun

Disclosed are an interposer and a chip package structure. The interposer may include: at least one signal transmission vias; at least one insulator isolation rings, one of said insulator isolation rings encircling one of said signal transmission vias; and at least one reverse-biased PN junction isolation rings, one of said reverse-biased PN junction isolation rings surrounding at least one of said insulator isolation rings, and the reverse-biased PN junction isolation ring including a semiconductor ring of a first conductivity type and a semiconductor ring of a second conductivity type from inside to outside, the semiconductor ring of the second conductivity type is connected to a bias potential.

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Shenzhen, China

Leqi Li