Lsi Logic Corporation

Lsi Corporation

Leonard Mora

Abiola A Awujoola

Clifford R Fishley

Abi Awujoola

Chok J Chia

Farshad Ghahghahi

Maurice O Othieno

Jeffrey A Hall

Amar Amin

Ed Fulcher

Abiola Awujoola

Maurice Othieno

An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.

Wire bond integrated circuit package for high speed I/O

A die package generally including (A) ground paths routing a power ground from a ground power set of contact pads in a first conductive layer to a ground ring in a second conductive layer, (B) core paths routing a core voltage from a core power set of contact pads in the first conductive layer to a core ring in the second conductive layer, and (C) input/output voltage paths routing input/output voltages from an input/output power set of contact pads in the first conductive layer to an input/output ring in the second conductive layer, (i) the input/output ring surrounding the core ring, (ii) the ring being configured to power input and output circuits of the die, (iii) the input/output ring being split into ring segments isolated from each other and (iv) at least one particular ring segment having a length of less than a single connector pitch.

Ball grid array package layout supporting many voltage splits and flexible split locations

A semiconductor substrate having high density signal routing is provided. The semiconductor substrate may include first signal traces electrically connected to a first row of signal bonding pads and routed on a first layer of the substrate. In addition, the substrate may include second signal traces electrically connected to a second row of signal bonding pads and routed on a second layer of the substrate. The first layer may be arranged in a strip line configuration, and the second layer may be arranged in a micro strip line configuration. Alternatively, the second signal traces may be arranged in a strip line configuration. In an embodiment, the first and second signal traces may be routed as differential pairs with approximately equal trace lengths. In another embodiment, all of the first and second signal traces may be routed as differential pairs.

Integrated circuit package substrate with high density routing mechanism

A semiconductor substrate having multiple signal voltage power supplies is provided. The substrate may include a signal voltage power ring separated into segmented voltage supply connections laterally spaced across the upper surface of the substrate. In addition, the substrate may include a voltage supply plane formed within the substrate. The voltage supply plane may be separated into segmented planes. Vias may electrically connect the segmented voltage supply connections to the segmented planes. In an embodiment, at least 2 of the segmented planes may have different voltage supplies. For example, each of the segmented voltage supply connections are configurable to supply power to a portion of input/output drivers of an integrated circuit. Voltage supplies of the segmented planes may be determined based on voltage requirements of the portions of the input/output drivers.

Integrated circuit package substrate with multiple voltage supplies

A substrate of the type for receiving an integrated circuit and a mold cover. The mold cover covers a first portion of the substrate and leaves a second portion of the substrate exposed with a boundary edge between the first portion of the substrate and a second portion of the substrate. The substrate has electrically conductive traces and electrically conductive vias on an upper layer adjacent the mold cover. The electrically conductive traces do not cross the boundary edge on the upper layer of the substrate.

Active trace rerouting

A substrate for electrically connecting to an integrated circuit, where the integrated circuit has differential pairs of signals that are associated with differential pairs of integrated circuit contacts. Differential pairs of substrate contacts are disposed on a first substrate layer in alignment with the differential pairs of integrated circuit contacts. Differential pairs of vias are also disposed on the first substrate layer, and extend to at least one underlying substrate layer. The differential pairs of vias make electrical connections with the differential pairs of substrate contacts. Each via within a given one of the differential pairs of vias is disposed within a column with each other on the first substrate layer. The columns for each of the differential pairs of vias are in a substantially parallel arrangement one with another. Differential pairs of traces are disposed on the at least one underlying substrate layer. The differential pairs of traces make electrical connection with the differential pairs of vias. Each trace within a given one of the differential pairs of traces is disposed adjacent each other, and routed to a peripheral portion of the at least one underlying substrate layer in a substantially side by side arrangement.

Growing community of inventors

San Jose, CA, United States of America

Leonard Mora