Nvidia Corporation

Xilinx, Inc.

Apple Inc.

Leilei Zhang

Zuhair Bokharey

Abraham Fong Yee

Lan H Hoang

Ron Boja

Shantanu Kalchuri

Kumar Nagarajan

Dennis R Pyper

Meng Chi Lee

Raghunandan Chaware

Wyeman Chen

Ronilo Boja

Takayoshi Katahira

Hoa Lap Do

Laurene Yip

Maryam Rahimi

Jason P Marsh

Yashar Abdollahian

Pedro R Ubaldo

Flexible modules and methods of manufacture are described. In an embodiment, a flexible module includes a flex board formed in which a passivation layer is applied in liquid form in a panel level process, followed by exposure and development. An electronic component is then mounted onto the flex board and encapsulated in a molding compound that is directly on a top surface of the passivation layer.

Flex board and flexible module

Electronic assembly methods and structures are described. In an embodiment, an electronic assembly method includes bringing together an electronic component and a routing substrate, and directing a large area photonic soldering light pulse toward the electronic component to bond the electronic component to the routing substrate.

Selective soldering with photonic soldering technology

Electronic package structures and assembly methods are described. In an embodiment, an electronic package includes a die mounted face up on a bottom side of a package substrate, and a plurality of components on a top side of the package substrate. The plurality of components may be unmolded, and available for rework. Additional structures are included within the package substrate to provide mechanical rigidity and robustness to the package for warpage control.

System in package for lower z height and reworkable component assembly

Stacked circuit board structures are described. In an embodiment, a plurality of vertical devices serves as electrical interconnections between the first circuit board and the second circuit board. In an embodiment, a plurality of vertical interconnects or pins serve as electrical interconnections between the first circuit board and the second circuit board. The vertical interconnects or pins may be arranged side-by-side with a plurality of vertical or horizontal devices.

Vertical module and perpendicular pin array interconnect for stacked circuit board structure

A process for manufacturing a printed circuit board having high-density microvias formed in a thick substrate is disclosed. The method includes the steps of forming one or more holes in a thick substrate using a laser drilling technique, electroplating the one or more holes with a conductive material, wherein the conductive material does not completely fill the one or more holes, and filling the one or more plated holes with a non-conductive material.

Process for manufacturing a printed circuit board having high density microvias formed in a thick substrate

An integrated circuit package includes a packaging substrate, which has an electrically conductive grid formed on a dielectric layer, and an integrated circuit die electrically coupled to the electrically conductive grid at one or more locations. In this embodiment, the electrically conductive grid includes a plurality of electrically conductive portions, wherein each portion is electrically coupled to at least one other portion, and a plurality of void regions that are electrically non-contiguous and substantially free of electrically conductive material. One advantage of the integrated circuit package is that a packaging substrate that is reduced in thickness, and therefore rigidity, can still maintain planarity during operation. The electrically conductive grid formed on a dielectric layer in the packaging substrate can replace a power plane or a ground plane in the packaging substrate, thereby reducing stressed produced as a result of thermal expansion mismatch between materials in the packaging substrate.

Integrated circuit package with a conductive grid formed in a packaging substrate

Stiffening is provided for an electronic package assembly having a substrate. A first electronic package, having a first function, is electromechanically fastened to a first surface of the substrate with a first array of electrically conductive interconnects, which is disposed over a central area of the substrate first surface. A second electronic package, having a second function, is fastened to the first substrate surface with a second conductive interconnect array. At least a pair of the first array conductors is electrically coupled to at least a pair of the second array conductors for data/signal exchange and at least a component of the first electronic package interacts with at least a component of the second package. A metallic stiffener ring is disposed about an outer periphery of at least the central area of the substrate.

Stiffening electronic packages by disposing a stiffener ring between substrate center area and conductive pad

A packaging substrate, a packaged semiconductor device, a computing device and methods for forming the same are provided. In one embodiment, a packaging substrate is provided that includes a packaging structure having a chip mounting surface and a bottom surface. The packaging structure has at a plurality of conductive paths formed between the chip mounting surface and the bottom surface. The conductive paths are configured to provide electrical connection between an integrated circuit chip disposed on the chip mounting surface and the bottom surface of the packaging structure. The packaging structure has an opening formed in the chip mounting surface proximate a perimeter of the packaging structure. A stiffening microstructure is disposed in the opening and is coupled to the packaging structure.

Open solder mask and or dielectric to increase lid or ring thickness and contact area to improve package coplanarity

An integrated circuit system includes a heat spreader that is thermally coupled to a semiconductor chip and has a cavity or opening formed in the heat spreader. The cavity or opening is positioned so that capacitors and/or other passive components mounted to the same packaging substrate as the semiconductor chip are at least partially disposed in the cavity or opening. Because the passive components are disposed in the cavity or opening, the integrated circuit system has a reduced package thickness.

Low-profile chip package with modified heat spreader

A system, method, and computer program product are provided for producing a high bandwidth bottom package of a die-on-package structure. The method includes the steps of receiving a bottom package comprising a substrate material having a top layer and an integrated circuit die that is coupled to the top layer of the substrate material. A first set of pads is formed on the top layer of the substrate material and a layer of dielectric material is applied on a top surface of the bottom package to cover the integrated circuit die and the first set of pads.

Bottom package having routing paths connected to top package and method of manufacturing the same

One embodiment of the present invention sets forth an integrated circuit package including a substrate, an integrated circuit die, and a plurality of solder bump structures. The substrate includes a first plurality of interconnects disposed on a first surface of the substrate. The integrated circuit die includes a second plurality of interconnects disposed on a first surface of the integrated circuit die. The plurality of solder bump structures couple the first plurality of interconnects to the second plurality of interconnects. The first plurality of interconnects are configured to be substantially aligned with the second plurality of interconnects when the integrated circuit package is at a first temperature within a range of about 0&#xb0; C. to about &#x2212;100&#xb0; C. The first plurality of interconnects are configured to be offset from the second plurality of interconnects when the integrated circuit package is at a temperature above the first temperature.

Offset integrated circuit packaging interconnects

An integrated circuit package is described including a substrate, an integrated circuit die, a first plurality of solder bump structures, and a first plurality of variable-size solder bump structures. The first plurality of solder bump structures electrically couple the integrated circuit die to the substrate. The first plurality of variable-size solder bump structures are disposed on a bottom surface of the substrate. The first plurality of variable-size solder bump structures are sized to be substantially coplanar with a seating plane of the integrated circuit package.

Variable-size solder bump structures for integrated circuit packaging

One embodiment sets forth an integrated circuit package that includes a substrate, one or more devices mounted on the substrate, a layer of under-fill configured to secure the one or more devices on the substrate, and a solder trench formed in the substrate, where the aggregate volume of the solder trench is large enough to capture a flow of excess under-fill during fabrication. One advantage of the disclosed integrated circuit package is that the solder trench is used in lieu of solder dam structures, thereby allowing a stencil to be lowered closer to the substrate surface during fabrication, which facilitates depositing solder paste during fabrication.

Absorbing excess under-fill flow with a solder trench

An integrated circuit package includes a packaging substrate with an electrical connection pad formed thereon and an integrated circuit die coupled to the electrical connection pad. The electrical connection pad includes an electroplated surface finish layer, but does not include an electrical trace configured as a plating tail. Because the electrical connection pad is free of a plating tail, signal degradation caused by the presence of plating tails in the integrated circuit package is avoided.

Method for forming an integrated circuit package

Embodiments of the invention generally relate to package substrates for integrated circuits. The package substrates each include a core having electrically conductive vias therethrough. Build-up layers formed from dielectric materials having different compositions are disposed around the core and include interconnects formed therein for facilitating electrical connections between integrated circuits coupled to the package substrate. The dielectric materials are selected to allow finer interconnect geometries where desired, and to increase the rigidity, and thus planarity, of the package substrate. Exemplary dielectric materials include pre-impregnated composite fibers for increasing the rigidity of a package substrate, and Ajinomoto Build-up Film for allowing the formation finer interconnect geometries.

Growing community of inventors

Sunnyvale, CA, United States of America

Leilei Zhang