Yangtze Memory Technologies Co., Ltd.

Wuhan Tianma Micro-electronics Co., Ltd

Xiamen Tianma Micro-electronics Co., Ltd.

Wuhan University

Lei Li

Zhiliang Xia

Xinyu Liu

Wei Xu

Lei Xue

ZongLiang Huo

Zhipeng Wu

Tuo Li

Bingguo Wang

Hao Pu

Qiangmin Wei

Chao Shen

Junzhan Liu

Hai Song

Yuanzhou Zheng

Jingxin Cao

Shiquan Qin

Long Qian

Xuemeng Lv

Caiyu Wu

Yuan Yuan

A method includes forming a stack of alternating insulating layers and sacrificial layers over a substrate; forming a trench through the stack to uncover the substrate to expose lateral sides of the insulating layers and the sacrificial layers, the trench extending from a core area to a stair step area of the stack; forming a liner to cover the exposed lateral sides; removing the liner in the trenches within a first area of the core area and the stair step area to expose the lateral sides of the sacrificial layers of the stack within the first area; removing the sacrificial layers within the first area; removing the liner in the trenches within a second area of the core area and the stair step area to expose the lateral sides of the sacrificial layers of the stack within the second area; and removing the sacrificial layers within the second area.

Method for removing sacrificial layers of a stack of a three-dimensional semiconductor structure in two steps

Semiconductor fabrication methods and semiconductor devices are disclosed. According to some aspects, a memory device includes a memory stack having interleaved a plurality of conductive layers and a plurality of insulating layers on a substrate, and a channel structure extending vertically in the memory stack. The channel structure includes a semiconductor channel extending vertically in the memory stack and conductively connected to a source structure. The semiconductor channel includes polysilicon, and a grain size of the polysilicon ranges from 100 nm to 600 nm.

Ladder annealing process for increasing polysilicon grain size in semiconductor device

The present invention relates to the field of inland vessel identification and ranging technology, and discloses a method, system, medium, equipment and terminal for identifying and ranging inland vessels. In the stage of vessel identification, based on the classical YOLO-V4 network model, the MobileNetV1 network is used to replace the feature extraction network CSPDarknet53 of the YOLO-V4 model; In the stage of vessel ranging, a binocular stereo vision ranging model is established, and the FSRCNN is used for super-resolution reconstruction of the original image pairs to enhance the vessel feature information; the ORB algorithm is used to achieve feature detection and matching at the sub-pixel level to obtain the parallax value between image pairs, and the depth information of the vessel target is obtained by triangulation principle and coordinate conversion.

Method, system, medium, equipment and terminal for inland vessel identification and depth estimation for smart maritime

An array substrate, a display panel and a display device are provided. The array substrate includes a plurality of pixel circuits arranged in an array in a first direction and a second direction, where each pixel circuit includes a first semiconductor portion including a first node and a second node; a first reference signal line and a second reference signal line electrically connected to the first node and the second node, respectively; and a switch element formed by a second semiconductor portion and a control portion. In adjacent two pixel circuits in the second direction, the first node of one pixel circuit is connected to the second node of the other one pixel circuit through the second semiconductor portion. The control portion has an orthographic projection on a plane of the array substrate at least partially overlapping the second semiconductor portion.

Array substrate including switch element that includes control portion and semiconductor portion, and display panel and display device including the same

Provided are a display panel, a method for manufacturing a display panel, and a display device. The display panel includes: a base substrate; an insulating layer disposed on the base substrate; a first groove provided in a transition region, a first cover layer and a common light-emitting functional layer. The first groove at least partially surrounds a display region. The first groove includes a first portion and a second portion. An aperture of the second portion on a side adjacent to the first portion is less than an aperture of the first portion on a side adjacent to the second portion. The first cover layer includes a first sub-cover layer disposed on the side of the insulating layer away from the base substrate and a second sub-cover layer. The second sub-cover layer covers a sidewall of the second portion. The common light-emitting functional layer is disconnected at the first groove.

Display panel,having discontinuous common light-emitting functional layer, method for manufacturing a display panel, and display device

Aspects of the disclosure provide methods for polysilicon characterization. The method includes receiving image data of a polysilicon structure formed on a sample substrate. The image data is in a spatial domain and is generated by transmission electron microscopy (TEM). Further, the method includes extracting frequency spectrum of the image data in a frequency domain. Then, the method includes selecting a subset of the frequency spectrum that corresponds to characteristic of first crystal grains that are of a first orientation, and transforming the selected subset of the frequency spectrum to the spatial domain to construct a first spatial image for the first crystal grains of the first orientation.

Methods for polysilicon characterization

Growing community of inventors

Wuhan, China

Lei Li