International Business Machines Corporation

Telefonaktiebolaget Lm Ericsson (publ)

Ultratech, Inc.

Leena Paivikki Buchwalter

Stephen L Buchwalter

Paul Stephen Andry

Raymond R Horton

John Patrick Hummel

John Ulrich Knickerbocker

Christopher Vincent Jahnes

Jon Alfred Casey

Sung Kwon Kang

Anthony K Stamper

Gareth Geoffrey Hougham

Cornelia K Tsang

Paul David Agnello

Jennifer L Lund

Barbara Jean Luther

Anurag Jain

Yun Yu Wang

Kevin K Chan

Sampath Purushothaman

Timothy Joseph Dalton

Christian Lavoie

Katherine Lynn Saenger

Paul Alfred Lauro

Russell Alan Budd

Edmund Juris Sprogis

Da-Yuan Shih

Jane M Shaw

Steven Lorenz Wright

James L Speidell

Alessandro Cesare Callegari

Claudius Feger

Kamalesh K Srivastava

Terence Lawrence Kane

Chirag Suryakant Patel

Stephan Alan Cohen

Paul Stephen McLaughlin

Donald W Henderson

Teresita Ordonez Graham

Sherif Ahmed Goma

Ajay Prabhakar Giri

James F Ziegler

Jonathan H Griffith

Michael J Sullivan

Richard R Thomas

Matteo Flotta

Eric H Laine

Luc L Belanger

Valérie Anne Oberson

Kathleen Conlon Hinge

Dirk Karl Manger

Daniel C Edelstein

Hariklia Deligianni

Kevin Shawn Petrarca

Jeffrey Donald Gelorme

Xiao Hu Liu

George Frederick Walker

Donald Francis Canaperi

Alfred Viehbeck

Eric D Perfecto

Terrence Robert O'Toole

Thomas Anthony Wassick

Brian Richard Sundlof

Michael Wayne Lane

Charles Robert Davis

Matthew J Farinelli

Michelle Leigh Steen

Ronald Dean Goldblatt

Michael Berger

Jae M Park

James Anthony Tornello

John E Heidenreich, Iii

Michael Meixner

Sharon L Nunes

Luis M Ferreiro, Deceased

Domenico Tortorella

Kevin Shawn Petraraca

Jeffrey D Gelmore

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers

A microelectromechanical system (MEMS) resonator or filter including a first conductive layer, one or more electrodes patterned in the first conductive layer which serve the function of signal input, signal output, or DC biasing, or some combination of these functions, an evacuated cavity, a resonating member comprised of a lower conductive layer and an upper structural layer, a first air gap between the resonating member and one or more of the electrodes, an upper membrane covering the cavity, and a second air gap between the resonating member and the upper membrane.

Low temperature Bi-CMOS compatible process for MEMS RF resonators and filters

A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.

Laser release process for very thin Si-carrier build

A method of formation of a microelectromechanical system (MEMS) resonator or filter which is compatible with integration with any analog, digital, or mixed-signal integrated circuit (IC) process, after or concurrently with the formation of the metal interconnect layers in those processes, by virtue of its materials of composition, processing steps, and temperature of fabrication is presented. The MEMS resonator or filter incorporates a lower metal level, which forms the electrodes of the MEMS resonator or filter, that may be shared with any or none of the existing metal interconnect levels on the IC. It further incorporates a resonating member that is comprised of at least one metal layer for electrical connection and electrostatic actuation, and at least one dielectric layer for structural purposes. The gap between the electrodes and the resonating member is created by the deposition and subsequent removal of a sacrificial layer comprised of a carbon-based material. The method of removal of the sacrificial material is by an oxygen plasma or an anneal in an oxygen containing ambient. A method of vacuum encapsulation of the MEMS resonator or filter is provided through means of a cavity containing the MEMS device, filled with additional sacrificial material, and sealed. Access vias are created through the membrane sealing the cavity; the sacrificial material is removed as stated previously, and the vias are re-sealed in a vacuum coating process.

Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers

The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.

Centrifugal method for filing high aspect ratio blind mirco vias powdered materials for circuit formation

An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.

Method for precision assembly of integrated circuit chip packages

A method of producing flexible interconnections for integrated circuits, and, in particular, the forming of flexible or compliant interconnections preferably by a laser-assisted chemical vapor deposition process in semiconductor or glass substrate-based carriers which are employed for mounting and packaging multiple integrated circuit chips and selectively, other devices in the technology.

Method to create flexible connections for integrated circuits

Centrifugal method for filing high aspect ratio blind micro vias with powdered materials for circuit formation

A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

Silicon chip carrier with conductive through-vias and method for fabricating same

Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via at an elevated temperature. A supply chamber is introduced to administer the polymeric material at an elevated temperature, typically at a temperature high enough to liquefy the polymeric material. The polymeric material is introduced through heated supply lines under force from a pump, piston, or a vacuum held within said supply chamber.

Materials and method to seal vias in silicon substrates

This disclosure teaches a method of filling deep vias or capping deep conducting paste filled vias in silicon or glass substrate using laser assisted chemical vapor deposition of metals. This method uses a continuous wave or pulsed laser to heat the via bottom and the growing metal fill selectively by selecting the laser wavelength such that silicon and/or glass do not absorb the energy of the laser in any appreciable manner to cause deposition in the field. Alternatively holographic mask or an array of micro lenses may be used to focus the laser beams to the vias to fill them with metal. The substrate is moved in a controlled manner in the z-direction away from the laser at about the rate of deposition thus causing the laser heating to be focused on the surface region of the growing metal fill.

Silicon chip carrier with through-vias using laser assisted chemical vapor deposition of conductor

Microswitch, comprising a base element (G) with a contact surface (KG) and an electrode (EG), and a switching element (S) with a contact surface (KS) and an electrode (ES) disposed opposite the electrode (EG) of the base element (G) at a distance (g). The switching element (S) is provided with a spring constant and is connected at least with a part of its edge portion with the base element (G) in a fixed manner. The contact surfaces (KG, KS) form a switching contact which is closable against a reaction force caused by the spring constant by means of a voltage applied to the electrodes (EG, ES). The base element (G) and the switching element (S) each comprise an auxiliary electrode (HG, HS) at a distance (a) from the electrode (EG, ES), to which a voltage can be applied. For opening the switching contact the electrodes (EG, ES) have a first voltage potential (U ) and the auxiliary electrodes have a second voltage potential (U ) of the voltage. The voltage potentials (U , U ) effect an accumulation of positive and negative charge carriers on the surface portions of the electrodes (EG, ES) and the auxiliary electrodes (HG, HS) such that surface portions with positive and negative charge carriers are opposite each other in a lateral direction and surface portions with the same charge carriers are opposite each other in an orthogonal direction.

Microswitch with a micro-electromechanical system

The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure including a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.

Plasma treatment to enhance inorganic dielectric adhesion to copper

Growing community of inventors

Hopewell Junction, NY, United States of America

Leena Paivikki Buchwalter