Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

International Business Machines Corporation

Globalfoundries Inc.

Lee Wee Teo

Shyue Seng Tan

Elgin Kiok Quek

Jae Gon Lee

Chung Foong Tan

Elgin Kiok Boone Quek

Shailendra Mishra

Chung Woh Lai

Johnny Widodo

Zhao Lun

Chunshan Yin

Jeffrey Chee

Yong Meng Lee

Yung Fu Chong

Dong Kyun Sohn

Alain Chan

Shiang Yang Ong

Vincent Leong

Lap Chan

Purakh Raj Verma

Ming Zhu

Henry K Utomo

Sanford Chu

James Yong Meng Lee

Vincent Ho

Wai Kin Chim

Wee Kiong Choi

Vivian Ng

Cheng Lin Heng

A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate; implanting a well region, having a first conductivity, on the semiconductor substrate; patterning a gate oxide layer on the well region; implanting a source, having a second conductivity, at an angle for implanting under the gate oxide layer; selectively implanting a dopant pocket, having a third conductivity that is opposite the second conductivity, at the angle for forming the dopant pocket under the gate oxide layer; and implanting a drain, having the third conductivity, for forming a transistor channel asymmetrically positioned under the gate oxide layer.

Integrated circuit system with band to band tunneling and method of manufacture thereof

A method for forming a semiconductor device is disclosed. The method includes providing a substrate prepared with a second gate structure. An inter-gate dielectric is formed on the substrate and over the second gate. A first gate is also formed. The first gate is adjacent to and separated from the second gate by the inter-gate dielectric. The substrate is patterned to form a split gate structure with the first and second adjacent gates. The split gate structure is provided with an e-field equalizer adjacent to the first gate. The e-field equalizer improves uniformity of e-field across the first gate during operation.

Control gate

An integrated circuit system that includes: providing a substrate including a first region and a second region; forming a first device over the first region and a resistance device over the second region; forming a first dielectric layer and a second dielectric layer over the substrate; removing a portion of the second dielectric layer; and annealing the integrated circuit system to remove dopant from the resistance device.

Integrated circuit system employing resistance altering techniques

A method for fabricating a semiconductor device is presented. The method comprises providing a gate stack including a gate dielectric and gate electrode over a substrate. Stressor regions comprising stressor material incorporated into substitutional sites of the substrate are formed within the substrate on opposed sides of the gate stack. A first stressor layer having a first stress value is formed over the semiconductor device after forming the stressor regions followed by an anneal to memorize at least a portion of the first stress value in the semiconductor device, wherein the anneal is conducted at a low temperature.

Method for fabricating semiconductor devices using stress engineering

A method and structure for a memory device, such as a 1T-SRAM, having a capacitor top plate directly over a doped bottom plate region. An example device comprises the following. An isolation film formed as to surround an active area on a substrate. A gate dielectric and gate electrode formed over a portion of the active area. A source element and a drain element in the substrate adjacent to the gate electrode. The drain element is comprised of a drain region and a bottom plate region. The drain region is between the bottom plate region and the gate structure. A capacitor dielectric and a capacitor top plate are over at least portions of the bottom plate region.

Capacitor top plate over source/drain to form a 1T memory device

A method for forming a device is presented. A substrate prepared with a feature having first and second adjacent surfaces is provided. A device layer is formed on the first and second adjacent surfaces of the feature. A first portion of the device layer over the first adjacent surface includes nano-crystals, whereas a second portion of the device layer over the second adjacent surface is devoid of nano-crystals.

Memory cell with improved retention

A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.

Diffusion barrier and method of formation thereof

A hybrid orientation substrate includes a base substrate having a first orientation, a first surface layer having a first orientation disposed on the base substrate in a first region, and a second surface layer disposed on the base substrate in a second region. The second surface layer has an upper sub-layer having a second orientation, and a lower sub-layer between the base substrate and the upper sub-layer. The lower sub-layer having a first stress induces a second stress on the upper sub-layer.

Hybrid orientation substrate with stress layer

A method of manufacture of an integrated circuit system includes: providing a second layer between a first layer and a third layer; forming an active device over the third layer; forming the third layer to form an island region underneath the active device; forming the second layer to form a floating second layer with an undercut beneath the island region; and depositing a fourth layer around the island region and the floating second layer.

Integrated circuit system with a floating dielectric region and method of manufacture thereof

A semiconductor method includes providing a silicon semiconductor substrate. A gate and a plurality of source/drain regions are formed on the silicon semiconductor substrate to form at least one pFET. A silicon-germanium layer is formed over the plurality of source/drain regions. The germanium is condensed from the silicon-germanium layer to form a plurality of source/drains in the plurality of source/drain regions by forming an oxide layer over the silicon-germanium layer. An interlevel dielectric layer is formed over the gate and the source/drain regions. A plurality of contacts is formed in the interlevel dielectric layer to the gate and the plurality of source/drain regions.

Semiconductor system using germanium condensation

Embodiments of the invention provide a method of forming a field-effect-transistor (FET). The method includes implanting one or more n-type dopants to create one or more implanted regions with at least a portion of the implanted regions being designated as regions for forming source and drain extensions of the FET; activating the implanted regions; etching with a chlorine based etchant to create openings in the implanted regions, and forming the source and drain extensions by exptaxially growing embedded silicon germanium in the openings. Structure of a semiconductor field-effect-transistor made thereof is also provided.

Method of forming source and drain of field-effect-transistor and structure thereof

Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.

Modulation of stress in stress film through ion implantation and its application in stress memorization technique

An integrated circuit system is provided including providing a substrate, forming an isolation structure base in the substrate without removal of the substrate, and forming a first transistor in the substrate next to the isolation structure base.

Method of manufacture of an integrated circuit system with self-aligned isolation structures

A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.

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Singapore, Singapore

Lee Wee Teo