University of California

Transphorm Inc.

Japan Science and Technology Agency

Universitaet Bremen

Lee McCarthy

Umesh Kumar Mishra

Steven P DenBaars

Nicholas A Fichtenbaum

Akihiko Murai

Shuji Nakamura

Daniel Bryce Thompson

Christina Ye Chen

Yifeng Wu

Primit A Parikh

Likun Shen

Detlef Hommel

Carsten Kruse

Stephan Figge

Rakesh Lai

A III-N device is described has a buffer layer, a first III-N material layer on the buffer layer, a second III-N material layer on the first III-N material layer on an opposite side from the buffer layer and a dispersion blocking layer between the buffer layer and the channel layer. The first III-N material layer is a channel layer and a compositional difference between the first III-N material layer and the second III-N material layer induces a 2DEG channel in the first III-N material layer. A sheet or a distribution of negative charge at an interface of the channel layer and the dispersion blocking layer confines electrons away from the buffer layer.

High voltage III-nitride semiconductor devices

Embodiments of the present disclosure includes a III-N device having a substrate layer, a first III-N material layer on one side of the substrate layer, a second III-N material layer on the first III-N material layer, and a barrier layer disposed on another side of the substrate layer, the barrier layer being less electrically conductive than the substrate layer.

III-N device structures having a non-insulating substrate

An electrolysis transistor for providing high-density electrochemistry and products utilizing the same, and high-efficiency electrolysis and electrochemical processes is disclosed. The electrolysis transistor may comprise an electrolyte, one or more working electrodes for transferring charge to or from said electrolyte, and one or more gate structures for altering electrode over-voltage and modifying the barrier at the electrode-electrolyte interface, reducing the voltage necessary for electrolysis. An electrochemical or photo-electrochemical cell may incorporate one or more of these electrolysis transistors.

Electrolysis transistor

A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550&#xb0; C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor.

Method using low temperature wafer bonding to fabricate transistors with heterojunctions of Si(Ge) to III-N materials

An (Al, Ga, In)N and ZnO direct wafer bonded light emitting diode (LED), wherein light passes through electrically conductive ZnO. Flat and clean surfaces are prepared for both the (Al, Ga, In)N and ZnO wafers. A wafer bonding process is then performed between the (Al, Ga, In)N and ZnO wafers, wherein the (Al, Ga, In)N and ZnO wafers are joined together and then wafer bonded in a nitrogen ambient under uniaxial pressure at a set temperature for a set duration. After the wafer bonding process, ZnO is shaped for increasing light extraction from inside of LED.

Method for fabricating a direct wafer bonded optoelectronic device

(Al,Ga,In)N and ZnO direct wafer bonded structure for optoelectronic applications, and its fabrication method

A method for producing a wafer bonded structure between (Al, In, Ga)N and Zn(S,Se). A highly reflective and conductive distributed Bragg reflector (DBR) for relatively short optical wave lengths can be fabricated using Zn(S,Se) and MgS/(Zn, Cd)Se materials. Using wafer bonding techniques, these high-quality DBR structures can be combined with a GaN-based optical device structure.

Method for wafer bonding (A1, In, Ga)N and Zn(S, Se) for optoelectronic applications

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Santa Barbara, CA, United States of America

Lee McCarthy