Qualcomm Incorporated

Layal Rouhana

Houssam Jomaa

Kuiwon Kang

Ravindra Vaman Shenoy

Omar James Bchir

Rajneesh Kumar

Mete Erturk

Donald William Kidwell, Jr

David Fraser Rae

Donald William Kidwell

Christopher Bahr

Seongryul Choi

A package that includes a substrate comprising an interposer interconnect and a cavity, a redistribution portion coupled to the substrate, the redistribution comprising a plurality of redistribution interconnects, and a first die coupled to the redistribution portion through the cavity of the substrate. A substantial region between a side surface of the first die and the substrate is free of an encapsulation layer. In some implementations, the substrate is free of a metal ring that surrounds the first die. In some implementations, the redistribution portion comprises a barrier layer and a first interconnect coupled to the barrier layer. The barrier layer is coupled to the interposer interconnect.

Low profile integrated package

A device comprising a semiconductor die, a package substrate coupled to the semiconductor die, and an encapsulation layer that at least partially encapsulates the semiconductor die. The package substrate includes at least one stacked via. The at least one stacked via includes a first via and a second via coupled to the first via. The second via includes a seed layer coupled to the first via. The second via includes a different shape than the first via. The package substrate includes a prepreg layer. The package substrate includes a first pad coupled to the first via, and a second pad coupled to the second via.

Integrated circuit (IC) package and package substrate comprising stacked vias

An integrated device package includes a die and a package substrate. The package substrate includes at least one dielectric layer (e.g., core layer, prepeg layer), a magnetic core in the dielectric layer, a first plurality of interconnects configured to operate as a first protective ring, and a second plurality of interconnects configured to operate as a first inductor. The second plurality of interconnects is positioned in the package substrate to at least partially surround the magnetic core. At least one interconnect from the second plurality of interconnects is also part of the first plurality of interconnects. In some implementations, the first protective ring is a non-contiguous protective ring. In some implementations, the first inductor is a solenoid inductor. In some implementations, the magnetic core includes a carrier, a first magnetic layer, and a second magnetic layer.

Integrated device package comprising a magnetic core inductor with protective ring embedded in a package substrate

Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder resist layer coupled to the first solder resist layer, and an opening in the first and second solder resist layers, the opening comprising a sidewall completely covered with the second solder resist layer, where a sidewall of the second solder resist layer covers a sidewall of the first solder resist layer. In some implementations, the opening is at least partially filled with an electrically conductive material. The electrically conductive material includes one of solder and/or an interconnect. The integrated device includes a first interconnect coupled to the electrically conductive material. The first interconnect is one of at least a solder, and/or an interconnect ball. In some implementations, the integrated device includes a pad coupled to the substrate, and a first interconnect coupled to the pad.

Package on package (PoP) integrated device comprising a plurality of solder resist layers

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San Diego, CA, United States of America

Layal Rouhana