Fairchild Semiconductor Corporation

Lay Yeap Lim

David Chong

Rajeev Dinkar Joshi

Chung-Lin Wu

Oseob Jeon

Maria Cristina B Estacio

Venkat Iyer

Boon Huan Gooi

Yoonhwa Choi

Byoung-Ok Lee

Tan Teik Keng

Shibaek Nam

Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Semiconductor die package and method for making the same

A lead frame with patterned conductive runs on the top surface to accept a wire bonded or flip-chip or COL configuration is disclosed. The top pattern is completed and the bottom is etched away creating cavities. The cavities are filled with a pre-mold material that lend structural support of the lead frame. The top is then etch through the lead frame to the pre-mold, except with the top conductive runs exist. In this manner the conductive runs are completed and isolated from each other so that the placement of the runs is flexible. The chips are mounted and the encapsulated and the lead frames are singulated. The pattern on the top and the bottom may be defined by first plated the patterns desired.

Method of making and designing lead frames for semiconductor packages

A leadframe structure is disclosed. The leadframe structure includes a first leadframe structure portion with a first thin portion and a first thick portion, where the first thin portion is defined in part by a first recess. It also includes a second leadframe structure portion with a second thin portion and a second thick portion, where the second thin portion is defined in part by a second recess. The first thin portion faces the second recess, and the second thin portion faces the first recess.

Etched leadframe structure

Etched leadframe structure including recesses

Growing community of inventors

Penang, Malaysia

Lay Yeap Lim