Intel Corporation

Lawrence S Uzelac

Andrew M Volk

Leakage current in semiconductor logic can be minimized using the present systems and techniques. For example, a CMOS circuit for low leakage battery operation can connect a real time clock to the power supply when available or to a low leakage source when the power supply is not available.

Method and apparatus for minimizing leakage current in semiconductor logic

A CMOS circuit for low leakage battery operation connects the real time clock to the power supply when available or to a low leakage source when the power supply is not available.

Method and apparatus for reducing sub-threshold off current for a real time clock circuit during battery operation

The invention provides, in an embodiment, a structure, method and means for generating clock phases, synchronized to the system clock, that to first order are independent of process parameters including drive current, parasitic resistance and parasitic capacitance. In one aspect, an apparatus is provided to generate an output phase at a predetermined time relative to an input clock signal and dependent on a logic phase width of the input clock signal. In another aspect, the apparatus includes similar circuit components with unequal units, the predetermined time is further dependent on the units ratio of the similar circuit components. In another aspect, the apparatus is cascaded with at least one reproduction of the apparatus, and configured to provide a multiple of the input clock signal. In another aspect, the apparatus is coupled in parallel with at least one reproduction of the apparatus, and configured to provide at least two output phases generated in parallel during the input clock signal.

Circuit in which the time delay of an input clock signal is dependent only on its logic phase width and a ratio of capacitances

According to some embodiments, a drive circuit provides an output resistance substantially stable despite variations in operating temperature.

Temperature compensated output driver

A power-up reference circuit and related method that generates a reference voltage in response to the circuit being powered up. The circuit includes a power-up sensing circuit that generates a set signal, a latch to generate and sustain the reference voltage in response to the set signal, and a reset key decoder to receive an N-bit key and in response thereto generate a reset signal that causes the latch to reset. Upon the circuit being powered up, the power-up sensing circuit generates the set signal which sets the latch to generate the reference voltage. The reference voltage can be used by other circuits to initialize their operating conditions. Once the reference voltage has been used, the N-bit key is generated which causes the decoder to generate the reset signal, which in turn, causes the latch to reset. When the latch is reset, the power-up reference circuit consumes substantially no power.

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Auburn, CA, United States of America

Lawrence S Uzelac