Intel Corporation

Other

Intel Corporatiion

Lawrence D Wong

Grant M Kloster

Jack T Kavalieros

Ebrahim Andideh

Jihperng Leu

Andrew W Ott

Tahir Ghani

Matthew V Metz

Van H Le

Abhishek A Sharma

Patrick R Morrow

Christopher J Jezewski

Steven N Towle

Indrajit Banerjee

Robert S Chau

Gilbert W Dewey

Mark L Doczy

Benjamin Chu-Kung

Suman Datta

Justin K Brask

Seung Hoon Sung

Valery M Dubin

David J Michalak

Scott Bruce Clendenning

Martin E Lee

Miriam Ruth Reshotko

Matthew Strecker Burriesci

Andrew P McMahon

Arnab Sen Gupta

Donald D Danielson

Phi L Nguyen

Bo Han

Ryan E Arch

Lawrence Foley

Sarah Bowen

Erin Culek

Steven Towie

Patrick Marrow

Ande Kitamura

Marnie L Harker

Disclosed herein are transistor electrode-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor electrode-channel arrangement may include a channel material, source/drain electrodes provided over the channel material, and a sealant at least partially enclosing one or more of the source/drain electrodes, wherein the sealant includes one or more metallic conductive materials.

Metallic sealants in transistor arrangements

Embodiments herein describe techniques for a semiconductor device including a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a conductive contact stack above the substrate and in contact with the channel layer, and a gate electrode separated from the channel layer by a gate dielectric layer. The conductive contact stack may be a drain electrode or a source electrode. In detail, the conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the conductive contact stack. Other embodiments may be described and/or claimed.

Contact stacks to reduce hydrogen in thin film transistor

A method and system for making financial or medical decisions. The method comprises training sets of models using classification training with sets of data derived from segregated data sources. Overall weighting of each model within the sets of models are determined for each of the sub-datasets. The sets of models, the overall weighting of each model and a number of examples provided from the data for each of the datasets are transmitted to a central server over a communication network, wherein the central server is configured to determine the relative weights of each of the sets of models in the overall ensemble model based on the number of examples, combine the sets of models, receive new application data, and predict at least one of outcome variables, an uncertainty factor for the variables, and drivers of the outcome variables based on the new application data.

Method and system for generating and aggregating models based on disparate data from insurance, financial services, and public industries

Embodiments of the invention provide transistor structures and interconnect structures that employ carbon nanotubes (CNTs). Further embodiments of the invention provide methods of fabricating transistor structures and interconnect structures that employ carbon nanotubes. Deterministic nanofabrication techniques according to embodiments of the invention can provide efficient routes for the large-scale manufacture of transistor and interconnect structures for use, for example, in random logic and memory circuit applications.

Carbon nanotube semiconductor devices and deterministic nanofabrication methods

Embodiments of the invention include a device with stacked substrates. Conducting interconnecting structures of one substrate are bonded to conducting interconnecting structures of another substrate. A passivating layer may be on the conducting interconnecting structures between the substrates and may be formed by an atomic layer deposition process or a with a Langmuir-Blodgett technique.

Thin passivation layer on 3D devices

A method and apparatus are provided an interconnect cladding layer. In one embodiment, a first sacrificial layer is deposited over a substrate and patterned. In the vias created during the patterning operation, a conductive material is placed to create conductive interconnects. After planarizing the conductive material, the sacrificial layer is removed leaving the interconnect exposed. A cladding layer is then deposited over the conductive material.

Method of making semiconductor device using a novel interconnect cladding layer

Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The trenches may be filled with metal by surface activating using a catalytic metal, followed by electroless deposition of a seed layer followed by superconformal filling bottom up.

Forming dual metal complementary metal oxide semiconductor integrated circuits

The invention relates to a microelectronic device and a structure therein that includes a diffusion barrier layer having a first thickness and a first dielectric constant. An etch stop layer is disposed above and on the diffusion barrier layer. The etch stop layer has a second thickness and a second dielectric constant.

Structure in a microelectronic device including a bi-layer for a diffusion barrier and an etch-stop layer

Highly porous, low-k dielectric materials are mechanically reinforced to enable the use of these low-k materials as intralayer and interlayer dielectrics in advanced integrated circuits such as those which incorporate highly porous materials in a Cu damascene interconnect technology. An integrated circuit, embodying such a mechanically reinforced dielectric layer generally includes a substrate having interconnected electrical elements therein, a copper-diffusion barrier or etch stop layer disposed over the substrate, the copper-diffusion barrier or etch stop layer being patterned so as to provide a plurality of electrically insulating structures, and a low-k dielectric layer disposed around the plurality of structures. A process, for making a mechanically reinforced, highly porous, low-k dielectric layer, generally includes forming a copper-diffusion or etch stop layer on a substrate, patterning the copper-diffusion or etch stop layer such that a plurality of structures are formed, the structures each having a top surface, forming a low-k dielectric layer over and adjacent to the structures, the low-k dielectric layer having a top surface, and polishing the low-k dielectric layer such that its top surface is substantially even with the top surfaces of the structures. The structures may be rectangular posts, or more geometrically complex forms. The structures may be identical, or a combination of various forms.

Structural reinforcement of highly porous low k dielectric films by Cu diffusion barrier structures

A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.

Dual-damascene interconnects without an etch stop layer by alternating ILDs

Highly porous, low-k dielectric materials are mechanically reinforced to enable the use of these low-k materials as interlayer dielectrics in advanced integrated circuits such as those which incorporate highly porous ILD materials in a Cu damascene interconnect technology. An integrated circuit, embodying such a mechanically reinforced ILD generally includes a substrate having interconnected electrical elements therein, a first dielectric layer disposed over the substrate, a plurality of electrically insulating structures disposed on the first dielectric layer, and a second dielectric layer disposed on the first dielectric layer such that the second dielectric surrounds the plurality of structures. A process, for making a mechanically reinforced, highly porous, low-k ILD, generally includes forming a first dielectric layer on a substrate, patterning the first dielectric layer such that a plurality of structures are formed, the structures each having a top surface, forming a second dielectric layer over and adjacent to the structures, the second dielectric layer having a top surface, and polishing the second dielectric layer such that its top surface is substantially even with the top surfaces of the structures. The structures may be rectangular posts, or more geometrically complex forms. The structures may be identical, or a combination of various forms.

Structural reinforcement of highly porous low k dielectric films by ILD posts

A low dielectric constant material having a first fluorine concentration in a near-surface portion and a second fluorine concentration in an interior portion provides an insulator suitable for use in integrated circuits. In a further aspect of the present invention, fluorine is depleted from a near-surface portion of a fluorine containing dielectric material by a reducing plasma. Fluorine in fluorinated low-k dielectric materials, such as SiOF, amorphous fluorinated carbon (a-F:C) and parylene-AF4, can react with surrounding materials such as metals and SiN, causing blisters and delamination. Treatment of these fluorinated low-k dielectric materials in a reducing plasma, which may be produced from precursor gases such as Hor NH, depletes the surface region of fluorine and hence reduces reaction with surrounding materials and F outgassing. By selecting an appropriate point in the integration flow, specific interfaces which are most susceptible to F-attack can be targeted for depletion.

Plasma induced depletion of fluorine from surfaces of fluorinated low-k dielectric materials

A method of forming an integrated circuit including forming a dielectric film is described. The forming of the dielectric film includes: providing a substrate, providing a carbon doped oxide film on the substrate, and treating the carbon doped oxide film with an electron beam. The carbon doped oxide film can be provided by chemical vapor deposition.

Electron-beam treated CDO films

A porous medium, such as a low dielectric constant film, can be made into an aggregate material to provide increased mechanical strength on a temporary basis. This can be achieved by, for example, a permeable modification treatment of the porous medium. By introduction of a secondary component into the void fraction of the porous medium, the mechanical properties are temporarily improved such that a porous film has mechanical characteristics similar to those of a much stiffer film. Methods in accordance with the present invention permit effective processing of highly porous interlayer dielectric (ILD) materials in a Cu damascene interconnect technology. Once a process operation such as a Cu chemical mechanical polishing (CMP) process, which requires greater mechanical strength than that provided by the porous film alone, is completed, the secondary component can be removed by methods such as displacement or dissolution.

Mechanically reinforced highly porous low dielectric constant films

A low dielectric constant material having a first fluorine concentration in a near-surface portion and a second fluorine concentration in an interior portion provides an insulator suitable for use in integrated circuits. In a further aspect of the present invention, fluorine is depleted from a near-surface portion of a fluorine containing dielectric material by a reducing plasma. Fluorine in fluorinated low-k dielectric materials, such as SiOF, amorphous fluorinated carbon (a-F:C) and parylene-AF4, can react with surrounding materials such as metals and Si N , causing blisters and delamination. Treatment of these fluorinated low-k dielectric materials in a reducing plasma, which may be produced from precursor gases such as H or NH , depletes the surface region of fluorine and hence reduces reaction with surrounding materials and F outgassing. By selecting an appropriate point in the integration flow, specific interfaces which are most susceptible to F-attack can be targeted for depletion.

Growing community of inventors

Beaverton, OR, United States of America

Lawrence D Wong