Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Stmicroelectronics Gmbh

International Business Machines Corporation

Stmicroelectronics S.a.

Globalfoundries Inc.

Stmicroelectronics (crolles 2) Sas

Commissariat a L'energie Atomique

Université´ D'aix-marseille

Centre National De La Recherche Scientifique

Imec

Universiteit Gent

Laurent Grenouillet

Maud Vinet

Yannick Le Tiec

Nicolas Posseme

Qing Liu

Yves Morand

Romain Wacquez

Kangguo Cheng

Bruce Bennett Doris

Ali Khakifirooz

Shay Reboh

Elisa Vianello

Marios Barlas

Olivier Rozeau

Nicolas J Loubet

Ajey Poovannummoottil Jacob

Pierre Morin

Cyrille Le Royer

Olivier Billoint

Philippe Galy

Jean-Marc Fedeli

Sébastien Kerdiles

Philippe Gilet

Frédéric Boeuf

Sylvain Maitrejean

Thomas Ernst

Sylvain Barraud

Christelle Charpin-Nicolle

Raluca Tiron

Alexei Tchelnokov

Louis Hutin

Tiphaine Dupont

Günther Roelkens

Dries Van Thourhout

Sebastien Barnola

Sotirios Athanasiou

François Marion

Carlo Cagli

Francois Rieutord

Anthonin Verdy

Jean-Michel Portal

François Rieutord

Jean Coignus

Alexandre Valentian

Philippe Blaise

Olivier Pollet

Marie-Anne Jaud

Jonathan Garcia

Benoit Sklenard

Sébastien Barnola

Nicolas Olivier

Olivier Faynot

Marion Perrin

François Rummens

Benoît Sklenard

Jerome Mazurier

Regis Orobtchouk

Philippe Regreny

Pedro Rojo-Romeo

Frédéric Milesi

Etienne Nowak

Lina Kadura

Vincent Mazzocchi

Thomas Mesquida

Boubacar Traore

Issam Ouerghi

Terry Francois

Liu Liu

Benoït Sklenard

Jérôme Mazurier

A data storage circuit includes an array of memory cells; a logic processing circuit configured to carry out a logic operation having N binary data as operands stored in N input memory cells, with N≥2, the second input/output nodes of the input memory cells being linked by a common bit line, the logic processing circuit comprising: a transimpedance amplifier stage configured to supply an analogue read signal from the voltage of the common bit line; a comparator intended to compare the analogue read signal with a first adjustable reference voltage in order to generate a digital output signal corresponding to the result of the logic operation; a control unit configured to adjust the reference voltage to an amplitude selected from among N distinct predetermined amplitudes, depending on the type of logic operation.

Data logic processing circuit integrated in a data storage circuit

A method for co-manufacturing a FeRAM and an OxRAM includes depositing a layer of first electrode carried out identically for a zone Zand a zone Z; depositing a layer of hafnium dioxide-based active material carried out identically for Zand Z; depositing a first conductive layer carried out identically for Zand Z; making a mask at Z, leaving Zfree; removing the layer at Z, with Zbeing protected by the mask; removing the mask at Z; and depositing a second conductive layer in contact with the layer at Zand in contact with the layer at Z, the material of the layer being chosen to create oxygen vacancies in the active layer and depositing a third conductive layer carried out identically for Zand Z

Method for co-manufacturing a ferroelectric memory and an OxRAM resistive memory and device co-integrating a ferroelectric memory and an OxRAM resistive memory

A method for increasing the surface roughness of a layer based on a metal having a catalytic power, includes fixing fluorine or chlorine on the surface of the metal based layer, by exposing the metal based layer to a plasma formed from a reactive gas containing fluorine or chlorine; exposing the surface of the metal based layer to a humid environment to produce an acid, by reaction of hydrogen from the humid environment with the fluorine or the chlorine fixed on the surface of the metal based layer, the acid reacting with the metal to form residues, the whole of the residues forming a pattern on the surface of the metal based layer, and etching the metal based layer through the residues, so as to transfer the pattern into the metal based layer.

Method for increasing the surface roughness of a metal layer

A method for increasing the surface roughness of a metal layer, includes depositing on the metal layer a sacrificial layer made of a dielectric material including nitrogen; exposing a surface of the sacrificial layer to an etching plasma so as to create asperities; and etching the metal layer through the sacrificial layer, so as to transfer the asperities of the sacrificial layer into a part at least of the metal layer.

A memory circuit includes a plurality of memory cells, each memory cell including a resistive memory element and a selection transistor of the FDSOI type connected in series with the resistive memory element. The selection transistor includes a channel region, a buried insulating layer, a back gate separated from the channel region by the buried insulating layer. The memory circuit further includes a circuit for biasing the back gate of the selection transistors, the biasing circuit being configured to apply a forward back-bias to the selection transistor of at least one memory cell during a programming or initialisation operation of the at least one memory cell.

Memory circuit comprising a plurality of 1T1R memory cells

A resistive memory cell may be provided with a first electrode and a second electrode arranged on either side of a dielectric layer and facing an interface between a first region and a second region, The first and second region may have different compositions in terms of doping and/or dielectric constant, so as to confine the zone of reversible creation of a conductive filament at the interface.

Resistive memory with a switching zone between two dielectric regions having different doping and/or dielectric constants

A matrix includes a plurality of volatile switches, each of the volatile switches including an active layer made of an OTS material, the plurality of volatile switches being divided into two groups in such a way as to form a message, each of the volatile switches of the first group having been initialized beforehand by an initialization voltage, none of the volatile switches of the second group having been initialized beforehand, the message being formed by the initialized or non-initialized states of each of the switches of the matrix.

Matrix of elementary switches forming a message, associated reading and writing methods

A method of production of a field-effect transistor from a stack of layers forming a semiconductor-on-insulator type substrate, the stack including a superficial layer of an initial thickness, made of a crystalline semiconductor material and covered with a protective layer, the method including: defining, by photolithography, a gate pattern in the protective layer; etching the gate pattern into the superficial layer to leave a thickness of the layer of semiconductor material in place, the thickness defining a height of a conduction channel of the field-effect transistor; forming a gate in the gate pattern; forming, in the superficial layer and on either side of the gate, source and drain zones, while preserving, in the zones, the initial thickness of the superficial layer.

Process for producing FET transistors

A resistive non-volatile memory cell includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, the memory cell being capable of reversibly switching between: &#x2014;a high resistance state obtained by applying a first bias voltage between the first electrode and the second electrode; and&#x2014;a low resistance state obtained by applying a second bias voltage between the first electrode and the second electrode; the oxide layer including a switching zone forming a conduction path prioritised for the current passing through the memory cell when the memory cell is in the low resistance state. The oxide layer includes a first zone doped with aluminium or silicon, the aluminium or silicon being present in the first zone with an atomic concentration that is selected so as to locate the switching zone outside the first zone.

Oxide-based resistive non-volatile memory cell and method for manufacturing same

A method of fabrication of a ferroelectric memory including a first electrode, a second electrode and a layer of active material made of hafnium dioxide HfOpositioned between the first electrode and the second electrode, where the method includes depositing a first electrode layer; depositing the layer of active material; doping the layer of active material; depositing a second electrode layer; wherein the method includes sub-microsecond laser annealing of the layer of doped active material.

Method for fabricating a ferroelectric memory and method for co-fabrication of a ferroelectric memory and of a resistive memory

A device for selecting a storage cell, includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, wherein the oxide layer is doped with a first element from column IV of the periodic table.

Device for selecting a memory cell

A photosensitive transistor device, on a semiconductor on insulator substrate, the photosensitive zone being formed in a substrate support layer and being arranged so that the concentration of photogenerated charges in the photosensitive zone can be increased towards a given zone facing the channel zone of the transistor.

Photosensitive detector with self-aligned 3D junction and gate

Field-effect transistor, the source and drain regions whereof are formed from a crystalline structure comprising:

Transistor having structured source and drain regions and production method thereof

The invention relates to a non-volatile memory that comprises selection transistors. Each selection transistor includes a layer of semiconductor material with a channel region and conduction electrodes, a gate stack including a gate electrode and a gate insulator, an isolation trench between the transistors, a storage structure of the RRAM type comprising a control electrode, and a dielectric layer formed under the control electrode and in the same material as the gate insulator, comprising a central part directly above the isolation trench and ends extending directly above conduction electrodes, and configured so as to form conducting filaments. The said storage structure and the said selection transistors are formed in the same pre-metallization layer.

Non-volatile memory allowing a high integration density

There is provided a method for producing on a same substrate at least one first transistor and at least one second transistor that have different characteristics, the method including producing at least one first gate pattern and at least one second gate pattern on the substrate; depositing, on the first and the second gate patterns, at least: a first protective layer, and a second protective layer overlying the first protective layer and made of a material different from that of the first protective layer; masking of the second gate pattern by a masking layer; isotropic etching of the second protective layer; removing the masking layer; and anisotropic etching of the second protective layer selectively relative to the first protective layer.

Method for producing on the same transistors substrate having different characteristics

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Rives, France

Laurent Grenouillet