Adeia Semiconductor Bonding Technologies Inc.

Agilent Technologies, Inc.

Other

Invensas Bonding Technologies, Inc.

Laura Wills Mirkarimi

Cyprian Emeka Uzoh

Rajesh Katkar

Gaius Gillman Fountain, Jr

Guilian Gao

Belgacem Haba

Ilyas Mohammed

Gabriel Z Guevara

Bongsub Lee

Liang Wang

David Ovrutsky

Arkalgud R Sitaram

Jeremy Alfred Theil

Kyong-Mo Bang

Vage Oganesian

Javier A DeLaCruz

Charles Gerard Woychik

Akash Agrawal

Tu Tam Vu

Xuan Li

Long Huynh

Reynaldo Co

Thomas Workman

Hong Shen

Annette Claire Grot

Mihail Sigalas

Ron Zhang

Bong-Sub Lee

Joy Watanabe

Steven L Teig

Scott Robert Summerfelt

Shaowu Huang

Giles Humpston

Eric Nequist

Stephen Roy Gilbert

Jun Amano

Willmar E Subido

Debabrata Gupta

Yukio Hashimoto

Suhail Jaan Sadiq

Luigi Colombo

Curt Alan Flory

Guoqiang Xing

Moshe Kriman

Trace Quentin Hurd

Ted S Moise

Chandrasekhar Mandalapu

Tomoyuki Sakoda

Pawel Mrozek

Christopher Aubuchon

George Carlton Hudson

Kai-Cheung Chow

Jr Gaius Gillman Fountain

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

Metal pads over TSV

Mitigating surface damage of probe pads in preparation for direct bonding of a substrate is provided. Methods and layer structures prepare a semiconductor substrate for direct bonding processes by restoring a flat direct-bonding surface after disruption of probe pad surfaces during test probing. An example method fills a sequence of metals and oxides over the disrupted probe pad surfaces and builds out a dielectric surface and interconnects for hybrid bonding. The interconnects may be connected to the probe pads, and/or to other electrical contacts of the substrate. A layer structure is described for increasing the yield and reliability of the resulting direct bonding process. Another example process builds the probe pads on a next-to-last metallization layer and then applies a direct bonding dielectric layer and damascene process without increasing the count of mask layers. Another example process and related layer structure recesses the probe pads to a lower metallization layer and allows recess cavities over the probe pads.

Mitigating surface damage of probe pads in preparation for direct bonding of a substrate

A device package comprising an integrated cooling assembly. The device package comprises a semiconductor device attached to a substrate and a cold plate attached to the semiconductor device. The cold plate's footprint is larger than the footprint of the semiconductor device so one or more portions of the cold plate extends past the edges of the semiconductor device's footprint. One or more standoffs are disposed adjacent to the semiconductor device to support the one or more portions of the cold plate that extend past the edges of the semiconductor device's footprint.

Cold plate and manifold integration for high reliability

Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

Techniques for processing devices

A bonded structure is disclosed. The bonded structure includes a first element that has a front side and a back side that is opposite the front side. The first element has a first conductive pad and a first nonconductive field region at the front side of the first element. The bonded structure also includes a second element that has a second conductive pad and a second nonconductive field region at a front side of the second element. The second conductive pad is bonded to the first conductive pad along an interface structure. The bonded structure also includes an integrated device that is coupled to or formed with the first element or the second element. The bonded structure further includes an elongate conductive structure that extends from the back side of the first element to the interface structure. The elongate conductive structure provides an effectively closed profile around the integrated device.

Sealed bonded structures and methods for forming the same

A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements. The differential expansion compensation structure can be configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.

Dimension compensation control for directly bonded structures

Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The cold plate has a perimeter sidewall, a top portion and pairs of opposing cavity sidewalls. The perimeter sidewall extends downwardly from the top portion to a backside of the semiconductor device to define a perimeter of the cold plate. Each pair of opposing cavity sidewalls extends downwardly from the top portion towards the backside of the semiconductor device to define a coolant chamber volume therebetween. A distance between each pair of opposing cavity sidewalls in a direction parallel with the backside of the semiconductor device defines a width of a corresponding coolant chamber volume and a spacing between adjacent coolant chamber volumes, wherein the ratio of width to spacing is about 1:1.

Fluid channel geometry optimizations to improve cooling efficiency

A bonded structure with protective semiconductor elements including a semiconductor element with active circuitry and a protective element including an obstructive layer and/or a protective circuitry layer. The obstructive layer is configured to inhibit external access to at least a portion of the active circuitry. The protective circuitry layer is configured to detect or disrupt external access to the protective element and/or the active circuitry of the semiconductor element. The semiconductor element and the protective element are directly bonded without an adhesive along a bonding interface.

Protective semiconductor elements for bonded structures

A method of manufacturing a device package. The method comprises patterning a first substrate to form patterned regions comprising a thermal oxide layer. The method further comprises directly bonding the patterned regions of the first substrate to a second substrate to form a bonding interface. The bonded first and second substrates form an integrated cooling assembly comprising a coolant chamber volume. Portions of the first substrate exposed to the coolant chamber volume comprise a native oxide layer.

Integrated cooling assemblies for advanced device packaging and methods of manufacturing the same

Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

Direct bonded stack structures for increased reliability and improved yield in microelectronics

A multi-component device package comprising an integrated cooling assembly and methods for manufacturing said multi-component device package. A multi-component device package may comprise a plurality of semiconductor devices encapsulated in a mold material. A portion of the mold material may be removed to expose the backside of at least one semiconductor device of the plurality of semiconductor devices. A first dielectric layer may be formed on the exposed backside of the at least one semiconductor device. A cold plate comprising a base plate may be prepared and then the base plate may be directly bonded to the exposed backside of the at least one semiconductor device.

Structures and methods for integrated cold plate in XPUs and memory

In some implementations, a device package may include a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. The integrated cooling assembly may include a semiconductor device and a cold plate having a first side attached to the semiconductor device and a second side opposite the first side. An adhesive layer may be disposed between the package cover and the second side of the cold plate, and one or more surfaces of second side of the cold plate may be spaced apart from the package cover to define a coolant channel therebetween. The adhesive layer may seal the package cover to the cold plate around a perimeter of the coolant channel.

Embedded cooling systems with coolant channel for device packaging

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a through-silicon via (TSV) may be disposed through at least one of the microelectronic substrates. The TSV is exposed at the bonding interface of the substrate and functions as a contact surface for direct bonding.

TSV as pad

A device package comprising a cooling system. The cooling system comprises a first substrate, a first semiconductor device located on a first region of the first substrate, a second semiconductor device located on a second region of the first substrate, a first cold plate attached to the first semiconductor device, a second cold plate attached to the second semiconductor device, and a manifold having a first chamber volume and a second chamber volume. The first chamber volume comprises a first inlet coupled to a first coolant line, a first outlet coupled to the first cold plate, and a second outlet coupled to the second cold plate. The second chamber volume comprises a third outlet coupled to a second coolant line, a second inlet coupled to the first cold plate, and a third inlet coupled to the second cold plate.

Manifold designs for embedded liquid cooling in a package

Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.

Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics and method for forming the same

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Sunol, CA, United States of America

Laura Wills Mirkarimi