Syntest Technologies, Inc.

Stardfx Technologies, Inc.

Laung-Terng Wang

Xiaoqing Wen

Po-Ching Hsu

Shianling Wu

Hsin-Po Wang

Nur A Touba

Khader S Abdel-Hafez

Zhigang Jiang

Hao-Jan Chao

Meng-Chyi Lin

Shyh-Horng Lin

Shih-Chia Kao

Ta-Chia Yeh

Sen-Wei Tsai

Xiaqing Wen

Jianping Yan

Boryau (Jack) Sheu

Fei-Sheng Hsu

Augusli Kifli

Ming-Tung Chang

Shun-Miin (Sam) Wang

Ravi Apte

Lizhen Yu

Michael S Hsiao

Fangfang Li

Feifei Zhao

Jinsong Liu

Hsin-P Wang

A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.

Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N&#x3e;1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.

Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-test

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults

A method and apparatus for generating a pseudorandom sequence using a hybrid ring generator with low hardware cost. When a primitive polynomial over GF(2) is selected as the characteristic polynomial f(x) to construct a hybrid ring generator, the circuit implementing f(x) will generate a maximum-length sequence (m-sequence). The hybrid ring generator offers unmatched benefits over existing linear feedback shift register (LFSR) based maximum-length sequence generators (MLSGs). Assume k 2-input XOR gates are required in a standard or modular LFSR design. These benefits include requiring only (k+1)/2 2-input XOR gates, having at most one level of a 2-input XOR gate between any pair of flip-flops, enabling the output of each flip-flop to drive at most 2 fanout nodes, and creating a highly regular structure that makes the new design more layout and timing friendly.

Method and apparatus for hybrid ring generator design

A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).

Computer-aided design system to automate scan synthesis at register-transfer level

A method and apparatus for testing a scan-based 3D integrated circuit (3DIC) using time-division demultiplexing/multiplexing allowing for high-data-rate scan patterns applied at input/output pads converting into low-data-rate scan patterns applied to each embeddded module in the 3DIC. A set of 3D design guidelines is proposed to reduce the number of test times and the number of through-silicon vias (TSVs) required for both pre-bond testing and post-bond testing. The technique allows reuse of scan patterns developed for pre-bond testing of each die (layer) for post-bond testing of the whole 3DIC. It further reduces test application time without concerns for I/O pad count limit and risks for fault coverage loss.

Method and apparatus for testing 3D integrated circuits

A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N&#x3e;1, includes the steps of: (a) generating and shifting-in N test stimuli to all scan cells within the N clock domains during a shift-in operation; (b) applying an ordered sequence of capture clocks to all scan cells within the N clock domains, the ordered sequence of capture clocks including a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all scan cells to locate any faults therein.

Multiple-capture DFT system to reduce peak capture power during self-test or scan test

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Sunnyvale, CA, United States of America

Laung-Terng Wang