Advanced Micro Devices Corporation

Larry Zhao

Paul Raymond Besser

Minh Van Ngo

Jeremy Isaac Martin

Hartmut Ruelke

Nicholas John Kepler

Christian Zistl

Eric M Apelgren

Jonathan B Smith

Donggang David Wu

A silicon nitride layer having a silicon-rich sub-layer and a standard sub-layer is formed on a copper surface to obtain excellent electromigration characteristics due to the standard sub-layer that is in contact with the copper, while maintaining a superior diffusion barrier behavior due to the silicon-rich sub-layer. By combining these sub-layers, the overall thickness of the silicon nitride layer may be kept small compared to conventional silicon nitride barrier layers, thereby reducing the capacitive coupling of adjacent copper lines.

Dielectric barrier layer for a copper metallization layer having a varying silicon concentration along its thickness

The electromigration resistance of nitride capped Cu lines is significantly improved by controlling the nitride deposition conditions to reduce the compressive stress of the deposited nitride layer, thereby reducing diffusion along the Cu-nitride interface. Embodiments include depositing a silicon nitride capping layer on inlaid Cu using dual frequency powers, holding the high frequency power constant and controlling the compressive stress of the deposited silicon nitride capping layer by varying the low frequency power to the susceptor, thereby enabling reduction of the compressive stress below about 2&#xd7;10Pascals. Embodiments also include sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a soft plasma containing NHdiluted with N, and then depositing the silicon nitride capping layer by plasma enhanced chemical vapor deposition, while varying the low frequency power between about 100 to about 300 watts. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.

Cu capping layer deposition with improved integrated circuit reliability

A metal interconnect structure and method for making the same provides an alloying elements layer that lines a via in a dielectric layer. The alloying element layer is therefore inserted at a critical electromigration failure site, i.e., at the fast diffusion site below the via in the underlying metal. Once the copper fill is performed in the via, an annealing step allows the alloying element to go into solid solution with the copper in and around the via. The solid solution of the alloying element and copper at the bottom of the via in the copper line improves the electromigration reliability of the structure.

Method of selectively alloying interconnect regions by deposition process

A metal interconnect structure and method of making the same implants ions of an alloy elements into a copper line through a via. Then ion implantation of the alloy elements in the copper line through the via provides improved electromigration properties at the copper line at a critical electromigration failure site, without attempting to provide alloy elements throughout the entire copper line.

Method of selectively alloying interconnect regions by ion implantation

A test circuit includes a wafer, an insulative layer formed on the wafer, and a plurality of test structures formed in the insulative layer. Each of the test structures comprises a first comb having a first plurality of fingers and a second comb having a second plurality of fingers. The first and second pluralities of fingers are interleaved to define a finger spacing between the first and second pluralities of fingers. The finger spacing in a first one of the test structures being different than the finger spacing in a second one of the test structures. A method for characterizing damage in a semiconductor device includes providing a wafer having an insulative layer and a plurality of test structures formed in the insulative layer. The test structures have different geometries. An electrical characteristic of first and second test structures of the plurality of test structures is determined. The electrical characteristics of the first and second test structures is compared. Damage to the insulative layer is characterized based on the comparison.

Method and test structure for characterizing sidewall damage in a semiconductor device

The electromigration resistance of nitride capped Cu lines is significantly improved by controlling the nitride deposition conditions to reduce the compressive stress of the deposited nitride layer, thereby reducing diffusion along the Cu-nitride interface. Embodiments include depositing a silicon nitride capping layer on inlaid Cu at a reduced RF power, e.g., about 400 to about 500 watts and an increased spacing, e.g., about 680 to about 720 mils, to reduce the compressive stress of the deposited silicon nitride layer to below about 2&times;10 Pascals. Embodiments also include sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a soft plasma containing NH diluted with N , ramping up the introduction of SiH and then initiating plasma enhanced chemical vapor deposition of a silicon nitride capping layer, while maintaining substantially the same pressure and N flow rate during plasma treatment, SiH ramp up and silicon nitride deposition. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.

Method of forming nitride capped Cu lines with reduced electromigration along the Cu/nitride interface

A method is provided for forming a conductive interconnect, the method comprising forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first conductive structure in the first opening. The method also comprises forming a second dielectric layer above the first dielectric layer and above the first conductive structure, forming a second opening in the second dielectric layer above at least a portion of the first conductive structure, the second opening having a side surface and a bottom surface, and forming at least one barrier metal layer in the second opening on the side surface and on the bottom surface. In addition, the method comprises removing a portion of the at least one barrier metal layer from the bottom surface, and forming a second conductive structure in the second opening, the second conductive structure contacting the at least the portion of the first conductive structure. The method further comprises forming the conductive interconnect by annealing the second conductive structure and the first conductive structure.

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Austin, TX, United States of America

Larry Zhao