Other

At&t Bell Laboratories

Agere Systems Guardian Corp.

Larry Ray Fenstermaker

Ilyoung Kim

Yervant Zorian

Frank P Higgins

James Louis Lewandowski

Jeffrey Jay Nagy

Kevin J O'Connor

A memory device has first and second sets of memory cells. Each of the cells in the second set is a neighboring cell corresponding to a respective cell of the first set. A data generating function generates a first pattern and a second pattern. A controller causes the first pattern to be written in the first set of memory cells, causes each cell in the second set of memory cells to be read simultaneously while the corresponding neighboring cell in the first set of memory cells is being written to, and causes a datum to be read from each cell in the second set of memory cells after the corresponding neighboring cell in the first set of memory cells is written to. An output data evaluator determines whether the data read from the second set of memory cells match the second pattern, and detects a fault in the memory device, if the data read do not match the second pattern.

Method and system for testing multiport memories

A dual-port RAM-type ring-address FIFO including a data input register with a set of transparent latches is tested by causing the FIFO to execute a test method comprised of a set of interwoven steps. Upon execution, the steps of the method cause the FIFO to manifest all possible memory, address and functional faults. This test method manifests faults by causing the FIFO to alter the state of various flags it normally sets and by altering the logic state of the data normally produced by the FIFO.

Method for built-in self-testing of ring-address FIFOs having a data

A first in, first out memory (FIFO) includes a multi-port memory array, which is accessed for read/write operations by activating a selected read or write word line. The read word line is controlled by a read shift register, and the write word line is controlled by a write shift register. In order to generate 'full' and 'empty' flags, the voltage state of read and write word lines are determined in 'match circuits', which compare the locations of the read and write pointers. This eliminates the use of counters, and allows the shift registers and word line match circuits to be an integral part of a single-block regular structure. Furthermore, it allows the FIFO to be readily expanded to multiple numbers of words and bits per word.

Fifo with word line match circuits for flag generation

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Nazareth, PA, United States of America

Larry Ray Fenstermaker