Taiwan Semiconductor Manufacturing Comp. Ltd.

Academia Sinica

Massachusetts Institute of Technology

National Chung Shan Institute of Science and Technology

Lain-Jong Li

Chao-Ching Cheng

Tse-An Chen

Syun-Ming Jang Jang

Tzu-Chiang Chen

Hung-Li Chiang

Tzu-Ang Chao

Chun-Chieh Lu

Ming-Yang Li

Chih-Piao Chuu

Chung-Chi Ko

Yi-Tse Hung

Wen-Hao Chang

Tien-I Bao

Shwang-Ming Jeng

Yu Chao Lin

Lih-Ping Li

Gregory Michael Pitner

Chien-Chih Tseng

Yung-Cheng Lu

Tung-Ying Lee

Jin Cai

Jing Kong

Shwangming Jeng

Tien I Bao

Yu-Huei Chen

Bi-Trong Chen

Jun-Lung Huang

Cheng-Te Lin

Ching-Yuan Su

Jeng-Cheng Liu

Shu E Ku

Shin-Wei Shen

Chen-Hua Douglas Yu

Weng Chang

Matthias Passlack

Martin Christopher Holland

Shen-Nan Lee

Cheng-Chung Lin

Zhen-Cheng Wu

Chih-Hsiang Yao

Timothy Vasen

Chao-Kai Wen

Yung-Chen Lu

Chuen-Ming Gee

Cheng Chung Lin

Ching-Jang Lin

Yi-Cheng Cheng

Bi-Troug Chen

Shwang Ming Jeng

Lung-Hao Hu

Tzu Ang Chao

Feng-Yu Wu

ChienChih Tseng

Tzeng-Lu Yeh

Ang-Yu Lu

Chih-Yu Wu

Keng-Ku Liu

Yumeng Shi

Christoph Hamsen

Han Yeh

Syun-Ming Jan

Shu-E Ku

Syan-Mang Jang

Yi-Hsien Lee

A semiconductor device includes a substrate, a channel layer, an insulating layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The channel layer over the substrate and includes two dimensional (2D) material. The insulating layer is on the channel layer. The source/drain contacts are over the channel layer. The gate dielectric layer is over the insulating layer and the channel layer. The gate electrode is over the gate dielectric layer and between the source/drain contacts.

Semiconductor device

A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.

CMOS fabrication methods for back-gate transistor

The present disclosure describes a method that includes forming a first two-dimensional (2D) layer on a first substrate and attaching a second 2D layer to a carrier film. The method also includes bonding the second 2D layer to the first 2D layer to form a heterostack including the first and second 2D layers. The method further includes separating the first 2D layer of the heterostack from the first substrate and attaching the heterostack to a second substrate. The method further includes removing the carrier film from the second 2D layer.

Semiconductor device with two-dimensional materials

A method of fabricating a semiconductor device includes applying a plasma to a portion of a metal dichalcogenide film. The metal dichalcogenide film includes a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. A metal layer including a second metal is formed over the portion of the metal dichalcogenide film after applying the plasma.

Semiconductor device and method of manufacturing semiconductor device

An array of rail structures is formed over a substrate. Each rail structure includes at least one bit line. Dielectric isolation structures straddling the array of rail structures are formed. Line trenches are provided between neighboring pairs of the dielectric isolation structures. A layer stack of a resistive memory material layer and a selector material layer is formed within each of the line trenches. A word line is formed on each of the layer stacks within unfilled volumes of the line trenches. The word lines or at least a subset of the bit lines includes a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement to provide a low resistivity conductive structure. An array of resistive memory elements is formed over the substrate. A plurality of arrays of resistive memory elements may be formed at different levels over the substrate.

Resistive memory devices using a carbon-based conductor line and methods for forming the same

A semiconductor structure includes a semiconductor substrate, a plurality of stacked units, a conductive structure, a plurality of dielectrics, a first electrode strip, a second electrode strip, and a plurality of contact structures. The stacked units are stacked up over the semiconductor substrate, and comprises a first passivation layer, a second passivation layer and a channel layer sandwiched between the first passivation layer and the second passivation layer. The conductive structure is disposed on the semiconductor substrate and wrapping around the stacked units. The dielectrics are surrounding the stacked units and separating the stacked units from the conductive structure. The first electrode strip and the second electrode strip are located on two opposing sides of the conductive structure. The contact structures are connecting the channel layer of each of the stacked units to the first electrode strip and the second electrode strip.

Semiconductor structure of stacked two-dimensional material layers

A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.

Fin field-effect transistor device with low-dimensional material and method

A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

Nano transistors with source/drain having side contacts to 2-D material

A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.

Semiconductor device and method of fabricating the same

A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

Method of manufacturing semiconductor devices including the steps of removing one or more of the nanotubes from the stack of nanotubes, and/or removing spacers that surrounds each of the plurality of nanotubes, and forming gate dielectric and/or gate electrode to the nanotubes

A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.

Transistors with channels formed of low-dimensional materials and method forming same

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Hsinchu, Taiwan

Lain-Jong Li