Applied Materials, Inc.

Applied Material, Inc.

Lai Zhao

Soo Young Choi

Yujia Zhai

Xiangxin Rui

Robin L Tiner

Jrjyan Jerry Chen

Jianheng Li

Gaku Furuta

Qunhua Wang

Shinichi Kurita

Allen K Lau

Jianhua Zhou

Beom Soo Park

Dong-Kil Yim

Jung Bae Kim

Tae Kyung Won

Sanjay D Yadav

Ilyoung R Hong

Dong Kil Yim

Changling Li

Hsiang An

David Atchley

Ganesh Babu Chandrasekaran

Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.

High-K dielectric materials comprising zirconium oxide utilized in display devices

A diffuser includes a front-side gradient surface formed from a diffuser block, a back-side gradient surface formed from the diffuser block, and opening structures formed from the front-side gradient surface to the back-side gradient surface. Each opening structure includes a conical opening having a first end along the front-side gradient surface and a second end corresponding to an apex at a depth within the diffuser block, and a cylindrical opening formed from the depth to the back-side gradient surface. The opening structures are arranged in rows including a first set of rows and a second set of rows alternately positioned along a length of the diffuser block.

Deposition chamber system diffuser with increased power efficiency

Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.

Hybrid high-K dielectric material film stacks comprising zirconium oxide utilized in display devices

In one implementation, a method for cleaning a processing chamber is provided. The method comprises introducing a reactive species into a processing chamber having a residual high-k dielectric material formed on one or more interior surfaces of the processing chamber. The reactive species is formed from a halogen-containing gas mixture and the one or more interior surfaces include at least one surface having a coating material formed thereon. The method further comprises reacting the residual high-k dielectric material with the reactive species to form a volatile product. The method further comprises removing the volatile product from the processing chamber. The removal rate of the residual high-k dielectric material is greater than a removal rate of the coating material. The high-k dielectric material is selected from zirconium dioxide (ZrO) and hafnium dioxide (HfO). The coating material includes a compound selected from alumina (AlO), yttrium-containing compounds, and combinations thereof.

Selective in-situ cleaning of high-k films from processing chamber using reactive gas precursor

Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrodeis disposed over the gate dielectric layer. The gate dielectric layer has a Dof about 5ecmeVto about 5ecmeVand a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

Process to reduce plasma induced damage

Disclosed herein is a sub-pixel circuit for a display device. The sub-pixel circuit has a driving TFT and at least one switching TFT. The at least one switching TFT is an oxide TFT. The sub-pixel circuit additionally has at least one storage capacitor wherein the storage capacitor has a capacitance between about 1 fF and about 55 fF.

Thin film transistor with small storage capacitor with metal oxide switch

The present disclosure relates to a gas confiner assembly designed to reduce the non-uniform deposition rates by confining the gas flow and changing the local gas flow distribution near the edge regions of the substrate. The material, size, shape and other features of the gas confiner assembly can be varied based on the processing requirements and associated deposition rates. In one embodiment, a gas confiner assembly for a processing chamber comprises a gas confiner configured to decrease gas flow and compensate for high deposition rates on edge regions of substrates. The gas confiner assembly also comprises a cover disposed below the gas confiner. The cover is configured to prevent a substrate support from being exposed to plasma.

Gas confiner assembly for eliminating shadow frame

Hybrid high-k dielectric material film stacks comprising zirconium oxide utilized in display devices

Embodiments of the present disclosure generally relate to a layer stack including a high K dielectric layer formed over a first dielectric layer and a metal electrode. The high K dielectric layer has a K value of 20 or higher and may be formed as a part of a capacitor, a gate insulating layer, or any suitable insulating layer in electronic devices, such as display devices. The layer stack includes a second dielectric layer disposed on the first dielectric layer and the metal layer, and the high K dielectric layer containing zirconium dioxide or hafnium dioxide disposed on the second dielectric layer. The second dielectric layer provides a homogenous surface on which the high K dielectric layer is formed. The homogeneous surface enables the high K dielectric material to be deposited uniformly thereover, resulting in a uniform thickness profile.

Layer stack for display applications

Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode is disposed over the gate dielectric layer. The gate dielectric layer has a Dof about 5ecmeVto about 5ecmeVand a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

High-k dielectric materials comprising zirconium oxide utilized in display devices

Methods for manufacturing a diffuser plate for a PECVD chamber are provided. The methods provide for applying a compliant abrasive medium to round the sharp edges at corners of the output holes on a contoured downstream side of a gas diffuser plate. By rounding the edges of the output holes reduces the flaking of deposited materials on the downstream side of the gas diffuser plate and reduces the amount of undesirable particles generated during the PECVD deposition process.

Growing community of inventors

Campbell, CA, United States of America

Lai Zhao