Industrial Technology Research Institute

Lai-Juh Chen

Chien-Mei Wang

Hsueh-Chung Chen

Shyh-Dar Lee

Hung-Wen Chiou

Shaw-Tzeng Hsia

Chung-I Chang

Chung Liang Chang

Shuo-Yen Chou

A method for forming a via hole, in an insulator layer, without the use of photoresist procedures, has been developed. A photosensitive, low dielectric constant layer, is used as an interlevel insulator layer, between metal interconnect structures. Direct exposure, of a specific region of the photosensitive, low dielectric constant layer, converts the a specific region of the photosensitive, low dielectric constant layer, to a material that remains insoluble in a specific solution, while an unexposed region, of the same layer, can be selectively removed, creating the desired via hole. A silicon oxide deposition, and an anisotropic dry etch procedure, are employed to protect exposed surfaces of the photosensitive, low dielectric constant layer, in the form of silicon oxide spacers, formed on the sides of the via hole, and a silicon oxide layer, overlaying the top surface of the photosensitive, low dielectric constant layer.

Sidewall protection for a via hole formed in a photosensitive, low dielectric constant layer

A new method is provided to treat the surface of a low-k material. The invention is specifically aimed at the improvement of the TaN barrier layer that is used in the deposition of a dual damascene structure. The invention uses e-beam exposure to improve the barrier metal (PVD TaN) properties for copper and low-k applications.

Method to improve the roughness of metal deposition on low-k material

A process for removing all amino groups adsorbed on a surface is described. The key feature of the invention is exposure of a layer, particularly an anti-reflection coating that has been deposited by means of PECVD, to a high-density plasma of either argon, oxygen, or a mixture of both. When this is done according to the teachings of the invention, all amino groups are removed from the surface and further processing of photoresist can then be initiated. Even if delays are introduced during subsequent further photoresist processing, dimensionally stable patterns are obtained.

Plasma treatment to improve DUV photoresist process

An improved and new apparatus and process for conditioning a chemical-mechanical polishing (CMP) pad has been developed, wherein sufficient conditioning is assured in order to restore the 'fresh pad' polish removal rate performance of the polishing pad, while at the same time prolong the life of the CMP polishing pad. The result is a lower cost process and improved product throughput for the CMP apparatus.

Chemical-mechanical polish (CMP) pad conditioner

A chemical mechanical polish (CMP) planarizing method for forming a planarized organo-functional siloxane polymer dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an organo-functional siloxane polymer dielectric layer. The organo-functional siloxane polymer dielectric layer is then partially treated with an oxygen containing plasma to form from the organo-functional siloxane polymer dielectric layer an oxygen containing plasma treated organo-functional siloxane polymer dielectric upper layer and an organo-functional siloxane polymer dielectric lower residue layer. Finally, the oxygen containing plasma treated organo-functional siloxane polymer dielectric upper layer is planarized through a chemical mechanical polish (CMP) planarizing method to form a planarized oxygen containing plasma treated organo-functional siloxane polymer dielectric upper layer.

Sequential oxygen plasma treatment and chemical mechanical polish (CMP)

A method and apparatus are described for Chemical Mechanical Polishing of wafers which achieves a constant removal rate of material from the wafer over the entire surface of the wafer. The wafer is held in a wafer carrier rotating at a wafer carrier angular velocity and is polished using a platen rotating at a platen angular velocity. The pressure exerted on the wafer by the wafer carrier is the largest at the wafer edge and smallest at the center of the wafer. The wafer carrier is divided into a number of wafer carrier circular segments so that the temperature of each wafer carrier circular segment can be controlled. The platen is divided into a number of platen circular segments so that the temperature of each platen circular segment can be controlled. The temperatures of the wafer carrier circular segments and the platen circular segments are then adjusted to provide a removal rate of material from the wafer which is uniform across the surface of the wafer.

Temperature compensated chemical mechanical polishing to achieve uniform

This invention describes a method of using Chemical Mechanical Polishing to planarize integrated circuit wafers using shallow trench isolation to provide isolation between devices in the wafer. After the material used to fill the shallow trenches has been formed a layer of Spin On Glass is formed over the material used to fill the shallow trenches. The polishing rate for the material used to fill the shallow trenches is at least twice as large as the polishing rate of the Spin On Glass. This difference in polishing rate causes the Spin On Glass to be the controlling factor in the overall polishing rate and a planar surface free of dishing or unwanted residue is achieved. In at least one of the embodiments the rate of change of the polishing pad temperature can be used to determine the end point of the polishing.

Method of planarizing wafers with shallow trench isolation

A method for making multilevel electrical interconnections having a planar intermetal dielectric (IMD) with low dielectric constant k and good thermal conductivity was achieved. The method involves patterning an electrically conductive layer to form metal lines on which is deposited an anisotropic plasma oxide (APO) resulting in a thin oxide on the sidewalls of the metal lines and a much thicker oxide on top of the lines. A low dielectric constant (k) polymer is deposited and the polymer and APO are chem/mech polished back to the top of the metal lines. A fluorine-doped silicon oxide (FSG) is deposited, and via holes are etched to provide electrical connections for the next level of interconnections. The APO provides wider openings between metal lines filled with the low k dielectric polymer thereby reducing the RC time delay of the circuit. The thick top APO provides more processing latitude for polishing back the APO and low k polymer. The FSG provides a lower dielectric constant k for further reducing the RC delay and a better thermal conductivity constant K for minimizing the Joule heating when the circuit is powered up. The process can be repeated several times to form a planar multilevel interconnection for completing wiring on the integrated circuit.

Method for fabricating intermetal dielectric insulation using

An improved and new process for chemical-mechanical polishing (CMP) of a substrate surface, wherein the endpoint for the planarization process is detected by monitoring the ratio of the rate of insulator material removal over a pattern feature to the rate of insulator material removal over an area without an underlying pattern feature, has been developed.

Chemical-mechanical polishing planarization monitor

Several quantities related to pad wear during chemical mechanical polishing have been improved by measuring the emissivity of the pad within the annulus of wear. This emissivity value is shown to relate directly to the amount of wear in the pad and is used to control the pressure on a conditioner that is employed to compensate for pad wear. By using multiple conditioners, each of which presses on the pad with a force that is related to the pad emissivity in its annulus of wear, the uniformity of material removal, both in time and space, is improved.

In situ method for CMP endpoint detection

A self contained unit for forming Cu metallurgy interconnection structures on SC substrates. The unit has an enclosed chamber with a plurality of apparatus for performing wet processes, including electroless metal plating and planarization. The unit provides a way of reducing the number of times the wafer is transferred between the wet process steps that require less environmental cleanliness and dry very clean processes steps.

Method and apparatus for forming very small scale Cu interconnect

An improved method of gap filling in the dielectric layer is described. Semiconductor device structures are formed in and on a semiconductor substrate and the top surface of the substrate is planarized. A conducting layer is deposited over the surface of the substrate and patterned. A layer of TEOS oxide is deposited over the patterned conducting layer by plasma enhanced chemical vapor deposition. While TEOS plasma residual remains on the wafer, the oxide is etched wherein the TEOS plasma protects the surface of the oxide layer. The combination of the TEOS deposition and etching processes results in a gap-filling dielectric.

Teos plasma protection technology

An improved and new process for chemical/mechanical planarization (CMP) of a substrate surface, wherein the endpoint for the planarization process is detected by monitoring the temperature of the polishing pad with an infrared temperature measuring device, has been developed. The process allows endpoint detection in-situ at the polishing apparatus, when polishing to remove a first layer of material and to stop the removal process when a second layer of material is exposed.

Chemical/mechanical polish (CMP) endpoint method

An improved and new process for chemical/mechanical planarization (CMP) of a substrate surface, wherein the removed layer thickness is detected, in-situ, without necessity to remove the substrate from the polishing apparatus has been developed. The method comprises monitoring the temperature of the polishing pad or the polished substrate versus polishing time, integrating the polishing temperature change versus polish time curve with polish time, and applying computer stored integration coefficients to the integrated area to derive the removed thickness.

Growing community of inventors

Hsin-Chu, Taiwan

Lai-Juh Chen