Samsung Electronics Co., Ltd.

Sungkyunkwan University

Seoul National University

Ulsan National Institute of Science and Technology

Research & Business Foundation Sungyunkwan University

Kyung-Eun Byun

Hyeonjin Shin

Keunwook Shin

Changhyun Kim

Hyunjae Song

Eunkyu Lee

Hyun-Jae Song

Sangwon Kim

Soyoung Lee

Sangwoo Kim

Jae-Ho Lee

Seongjun Park

Sangwook Kim

Changseok Lee

Yeonchoo Cho

Seong-jun Park

Hyun-jong Chung

Jin-seong Heo

David Seo

Jae-ho Lee

Seunggeol Nam

Minsu Seol

Taejin Park

Hyeon-jin Shin

Yonghoon Kim

Jae-Young Kim

In-kyeong Yoo

Taejin Choi

Minhyun Lee

Janghee Lee

Sangsoo Lee

Ho-jung Kim

Yunseong Lee

Sang-Woo Kim

Sang-woo Kim

Woojin Lee

Jong-Jin Park

Sanghoon Ahn

Kwanghee Lee

Alum Jung

Hyunseok Lim

Hyoungsub Kim

Jaehwan Jung

Wonsik Ahn

Hoijoon Kim

Mirine Leem

Hyung-cheol Shin

Jae-hong Lee

Ahrum Sohn

Hee-jun Yang

Yun-sung Woo

Jeonil Lee

Hyeonsuk Shin

Seokmo Hong

Junghoo Shin

Kaoru Yamamoto

Sungjoo An

Jungsoo Yoon

Sang-hun Jeon

Thanh Tien Nguyen

Dong Wook Lee

Taehyeong Kim

Minseok Yoo

Dong-Wook Lee

Kibum Kim

Minseok Shin

Junyoung Kwon

Ji-hyun Bae

Nae-eung Lee

Hyeon-Jin Shin

Do-il Kim

Jeeeun Yang

Moonil Jung

Van Luan Nguyen

Quang Trung Tran

Yun-Sung Woo

Euntae Kim

Pin Zhao

Geuno Jeong

Minhyuk Cho

Min-Hyun Lee

Hyun-Jong Chung

Jin-Seong Heo

Seong-Jun Park

Hee-Jun Yang

An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of the rest region of the semiconductor layer, a metal layer facing the semiconductor layer, a semi-metal layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the semi-metal layer and the semiconductor and covering the first region.

Interconnect structure to reduce contact resistance, electronic device including the same, and method of manufacturing the interconnect structure

Provided are nanocrystalline graphene and a method of forming the same. The nanocrystalline graphene may include a plurality of grains formed by stacking a plurality of graphene sheets and has a grain density of about 500 ea/μmor higher and a root-mean-square (RMS) roughness in a range of about 0.1 or more to about 1.0 or less. When the nanocrystalline graphene has a grain density and a RMS roughness with these ranges, nanocrystalline graphene capable of covering the entirety of a large area on a substrate as a thin layer may be provided.

Nanocrystalline graphene and method of forming nanocrystalline graphene

Provided are an interconnect structure and an electronic device including the same. The interconnect structure may include a conductive wiring having a certain pattern, a dielectric layer on side surfaces of the conductive wiring, a capping layer on the conductive wiring, and a graphene layer on the dielectric layer. The graphene layer may include a graphene material. A ratio of carbons having spbonds to carbons having spbonds in the graphene material is 1 or less.

Interconnect structure and electronic device including the same

A vertical channel transistor includes a first source/drain electrode; a second source/drain electrode spaced apart from the first source/drain electrode in a first direction; a first channel pattern between the first source/drain electrode and the second source/drain electrode; a first gate electrode on a side surface of the first channel pattern; a first gate insulation layer between the first channel pattern and the first gate electrode; and a first graphene insertion layer between the first source/drain electrode and the first channel pattern.

Vertical channel transistor including a graphene insertion layer beweeen a source/drain electrode and a channel pattern

Provided are a wiring including a graphene layer and a method of manufacturing the wiring. The method may include growing a graphene layer on a substrate and doping the graphene layer with a metal. The graphene layer may be grown using a plasma of a hydrocarbon at a temperature of about 200° C. to about 600° C. by plasma enhanced chemical vapor deposition (PECVD).

Wiring including graphene layer and method of manufacturing the same

Provided is a thin film structure including a substrate, a metal layer on the substrate and spaced apart from the substrate, and a two-dimensional material layer between the substrate and the metal layer. The two-dimensional material layer may be configured to limit and/or block an electron transfer between the substrate and the metal layer. A resistivity of a metal layer on the two-dimensional material layer may be lowered by the two-dimensional material layer.

Thin film structure and electronic device including two-dimensional material

A method of calculating a thickness of a graphene layer and a method of measuring a content of silicon carbide, by using X-ray photoelectron spectroscopy (XPS), are provided. The method of calculating the thickness of the graphene layer, which is directly grown on a silicon substrate, includes measuring the thickness of the graphene layer directly grown on the silicon substrate, by using a ratio between a signal intensity of a photoelectron beam emitted from the graphene layer and a signal intensity of a photoelectron beam emitted from the silicon substrate.

Method of calculating thickness of graphene layer and method of measuring content of silicon carbide by using XPS

Disclosed are an interconnect structure, an electronic device including the same, and a method of manufacturing the interconnect structure. The interconnect structure includes a dielectric layer; a conductive interconnect on the dielectric layer; and a graphene cap layer on the conductive interconnect. The graphene cap layer contains graphene quantum dots, has a carbon content of 80 at % or more, and has an oxygen content of 15 at % or less.

Interconnect structure, electronic device including the same, and method of manufacturing interconnect structure

Disclosed are an electronic device including a two-dimensional material, and a method of fabricating the electronic device. The electronic device may include a first metal layer including a transition metal, a second metal layer on the first metal layer and including gold (Au), and a two-dimensional material layer between the first metal layer and the second metal layer. The two-dimensional material layer may include a transition metal dichalcogenide (TMD). The two-dimensional material layer may be formed as a chalcogen element diffuses into the second metal layer and reacts with the transition metal of the first metal layer adjacent to the second metal layer.

Electronic device including two-dimensional material and method of fabricating the same

A method of forming a material film includes providing a non-photosensitive mask on a substrate to expose a partial region of the substrate, forming a material film on the partial region of the substrate using a sputtering process, removing the non-photosensitive mask, and heat-treating the substrate and the material film from which the non-photosensitive mask is removed under a first gas atmosphere. The material film includes a transition metal and a chalcogen element. The sputtering process may include an RF magnetron sputtering process. The heat treatment may be performed at a higher temperature than a temperature of the forming the material film.

Method of forming material layer

Provided are a metal chalcogenide thin film and a method and device for manufacturing the same. The metal chalcogenide thin film includes a transition metal element and a chalcogen element, and at least one of the transition metal element and the chalcogen element having a composition gradient along the surface of the metal chalcogenide thin film, the composition gradient being an in-plane composition gradient. The metal chalcogenide thin film may be prepared by using a manufacturing method including providing a transition metal precursor and a chalcogen precursor on a substrate by using a confined reaction space in such a manner that at least one of the transition metal precursor and the chalcogen precursor forms a concentration gradient according to a position on the surface of the substrate; and heat-treating the substrate.

Metal chalcogenide film and method and device for manufacturing the same

Provided are a vertical-channel cell array transistor structure and a dynamic random-access memory (DRAM) device including the same. The vertical-channel cell array transistor structure includes a semiconductor substrate, a plurality of channels arranged in an array on the semiconductor substrate and each extending perpendicularly from the semiconductor substrate, a gate insulating layer on the plurality of channels, a plurality of word lines on the semiconductor substrate and extending in a first direction, and a two-dimensional (2D) material layer on at least one surface of each of the plurality of word lines.

Vertical-channel cell array transistor structure and dram device including the same

A method of pre-treating a substrate on which graphene will be directly formed may include pre-treating the substrate using a pre-treatment gas including at least a carbon source and hydrogen.

Method of pre-treating substrate and method of directly forming graphene using the same

A semiconductor device is provided. The semiconductor device includes a metal layer, a semiconductor layer in electrical contact with the metal layer, a two-dimensional (2D) material layer disposed between the metal layer and the semiconductor layer and having a 2D crystal structure, and a metal compound layer disposed between the 2D material layer and the semiconductor layer.

Metal-to-semiconductor contact including a 2D crystal material layer

A stacked structure may include a first material layer, a two-dimensional material layer on the first material layer, and a second material layer on the two-dimensional material layer. The two-dimensional material layer may include a plurality of holes that each expose a portion of the first material layer. The second material layer may be coupled to the first material layer through the plurality of holes.

Stacked structure including two-dimensional material and method of fabricating the stacked structure

Growing community of inventors

Uijeongbu-si, South Korea

Kyung-Eun Byun