Intel Corporation

Micron Technology Incorporated

Nanosys, Inc.

Kyu S Min

Durai Vishak Nirmal Ramaswamy

Thomas M Graettinger

Ronald Allen Weimer

Nathan Franklin

Prashant Majhi

Wilman Tsai

Ron Weimer

Tejas Krishnamohan

Tom Graettinger

Arup Bhattacharyya

J Wallace Parce

Erik C Scher

William P Freeman

Jeffery A Whiteford

Mihai A Buretea

Noel Rocklein

Andreas Meisel

Rhett T Brewer

Qing Ma

Krishna Kumar Parat

Oleh Karpenko

Srivardhan Gowda

Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.

Thickened sidewall dielectric for memory cell

A discrete storage element film is disposed above a tunneling dielectric film against a shallow trench isolation structure and under conditions to resist formation of the discrete storage element film upon vertical exposures of the shallow trench isolation structure. A discrete storage element film is also disposed above a tunneling dielectric film against a recessed isolation structure. A microelectronic device incorporates the discrete storage element film. A computing system incorporates the microelectronic device.

Self-aligned charge-trapping layers for non-volatile data storage, processes of forming same, and devices containing same

Nanocrystal structures formed using atomic layer deposition (ALD) processes are useful in the formation of integrated circuits such as memory devices. Rather than continuing the ALD process until a continuous layer is formed, the ALD process is halted prematurely to leave a discontinuous formation of nanocrystals which are then capped by a different material, thus forming a layer with a discontinuous portion and a bulk portion. Such nanocrystals can serve as charge-storage sites within the bulk portion, and the resulting structure can serve as a floating gate of a floating-gate memory cell. A floating gate may contain one or more layers of such nanocrystal structures.

Method of forming layers using atomic layer deposition

A memory device has multiple dielectric barrier regions. A memory device has multiple barrier regions that provide higher or lower current-voltage slope compared to a memory device having a single barrier region. The device also has electrode regions that provide further control over the current-voltage relationship.

Multilayer dielectric memory device

Nanocrystal formation using atomic layer deposition and resulting apparatus

Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.

Memory cells containing charge-trapping zones

Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge-retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material.

Memory cells, methods of forming dielectric materials, and methods of forming memory cells

Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.

Floating gate structures

Memory cells, electronic systems, methods of forming memory cells, and methods of programming memory cells

Growing community of inventors

San Jose, CA, United States of America

Kyu S Min