Samsung Electronics Co., Ltd.

Kyu-pil Lee

Bong-Soo Kim

Yoo-Sang Hwang

Jin-bum Kim

Hyeong-sun Hong

Chang-hyun Cho

Gyo-young Jin

Yong-chul Oh

Joo-young Lee

Tae-jin Park

Yong-jik Park

Cheon-bae Kim

Jong-ryul Jun

Kuk-han Yoon

A device includes a substrate, a first electrode on the substrate, an insulating pattern on the substrate, a second electrode on an upper end of the insulating pattern, a two-dimensional (2D) material layer on a side surface of the insulating pattern, a gate insulating layer covering the 2D material layer, and a gate electrode contacting the gate insulting layer. The insulating pattern extends from the first electrode in a direction substantially vertical to the substrate. The 2D material layer includes at least one atomic layer of a 2D material that is substantially parallel to the side surface of the insulating pattern.

Device comprising 2D material

A semiconductor device including at least one first capacitor and at least one second capacitor. The at least one first capacitor includes a first storage node having a cylindrical shape. The at least one second capacitor includes a lower second storage node having a hollow pillar shape including a hollow portion, and an upper second storage node having a cylindrical shape and extending upward from the lower second storage node.

Semiconductor device having capacitors

An integrated circuit memory device includes a substrate divided into a cell array region, a core region, and a peripheral circuit region. A plurality of memory cells in the memory cell region each comprise a memory cell transistor having first spaced apart source/drain regions of the substrate with a predetermined conductivity. A sensing circuit in the core region of the substrate includes a sensing transistor having second spaced apart source/drain regions of the substrate. Each of the second source/drain regions includes high and low concentration regions of the predetermined conductivity wherein the high and low concentration regions are doped with a common dopant. A peripheral circuit in the peripheral region of the substrate includes a peripheral transistor having third spaced apart source/drain regions wherein each of the third source/drain regions has high and low concentration regions thereof. The high concentration region of the third source/drain regions has a first dopant and the low concentration region of the third source/drain region has a second dopant. Related methods are also discussed.

Method for forming integrated circuit memory devices with high and low

A DRAM cell is formed by forming a capped gate line on a substrate, including a gate line insulation layer on the substrate, a gate line on the gate line insulation layer and a gate line cap covering top and sidewall portions of the gate line. Spaced apart source/drain regions are formed in the substrate on opposite sides of the gate line. A dielectric region is formed covering the capped electrode. A storage electrode plug is formed extending from a surface of the dielectric region through the dielectric region and along a first sidewall portion of the gate line cap to contact a first of the source/drain regions. A channel electrode is formed extending from the surface of the dielectric region through the dielectric region and along a second sidewall portion of the gate line cap to contact a second of the source/drain regions. The channel electrode may include a channel line formed on a channel line insulation layer on the dielectric region and having a channel line extension extending through the channel line insulation layer into the dielectric region, and a channel electrode plug extending from the channel line extension to the second source/drain region.

Methods of fabrication DRAM transistor cells with a self-aligned storage

Integrated circuit memory devices with high and low dopant concentration

A semiconductor device and method for manufacturing the same includes a plurality of memory cells, each cell having a transistor formed on a first semiconductor substrate and comprising first and second impurity regions and a gate electrode, and a compacitor comprising a first electrode connected with the first impurity region of the transistor and a second electrode formed on the first electrode with a dielectric film disposed therebetween, wherein a channel region formed between the first impurity region and the second impurity region of the transistor is vertically located on the capacitor, and a contact hole connecting the second impurity region of the transistor with the bit-line is vertically located on the channel region, thus achieving the cell area required for one-giga-bit memory devices and beyond and enabling increased capacitance.

Isolated SOI memory structure with vertically formed transistor and

A DRAM cell is formed by forming a capped gate line on a substrate, including a gate line insulation layer on the substrate, a gate line on the gate line insulation layer and a gate line cap covering top and sidewall portions of the gate line. Spaced apart source/drain regions are formed in the substrate on opposite sides of the gate line. A dielectric region is formed covering the capped electrode. A storage electrode plug is formed extending from a surface of the dielectric region through the dielectric region and along a first sidewall portion of the gate line cap to contact a first of the source/drain regions. A channel electrode is formed extending from the surface of the dielectric region through the dielectric region and along a second sidewall portion of the gate line cap to contact a second of the source/drain regions. The channel electrode may include a channel line formed on a channel line insulation layer on the dielectric region and having a channel line extension extending through the channel line insulation layer into the dielectric region, and a channel electrode plug extending from the channel line extension to the second source/drain region. Alternatively, the channel electrode includes a channel line formed overlying the second source/drain region and extending to directly contact the second source/drain region. A channel line cap preferably covers top and sidewall portions of the channel line, and a storage electrode formed along a sidewall portion thereof.

DRAM transistor cells with a self-aligned storage electrode contact

A capacitor structure includes a substrate and an insulating layer on the substrate. The insulating layer has a contact hole therethrough extending from a surface of the substrate to a surface of the insulating layer opposite the substrate. A metal plug is provided in the contact hole, and a storage electrode is provided on the insulating layer in electrical contact with the metal plug. Accordingly, the storage electrode is electrically connected to the substrate through the metal plug. In particular, the metal plug preferably comprises a metal such as tungsten having a high melting point. Related methods are also disclosed.

Metal plug capacitor structures for integrated circuit devices and

A cell transistor for a dynamic random access memory cell (DRAM) is formed on a substrate, including a capped gate line formed on the substrate, spaced apart source/drain regions formed in the substrate disposed on opposite sides of the capped gate line, a capped channel line overlying and separated from the gate line by an intervening dielectric region and contacting a first of the source/drain regions through the intervening dielectric region, and a second dielectric region covering the capped channel line. To form a buried contact, the transistor is etched with an etchant which etches the intervening dielectric region and the second dielectric region at a first rate and gate line and channel line caps covering the gate and channel lines at a second rate, the first rate being greater than the second rate, for an etching time sufficient to expose a second of the source/drain regions while leaving the gate line and the channel line covered. The first etching rate preferably is at least 20 times greater than the second etching rate. Preferably, the gate line cap and the channel line cap each include silicon nitride, the first interlayer dielectric region includes silicon dioxide and one of borophosphosilicate glass or ozone-tetraethylorthosilicate (O.sub.3 -TEOS), the second dielectric region includes ozone-tetraethylorthosilicate (O.sub.3 -TEOS), the third interlayer dielectric region includes silicon dioxide, and the etchant includes C.sub.3 F.sub.8 gas or C.sub.4 F.sub.8 gas, applied at approximately 3 milliTorr to approximately 4 milliTorr.

Methods of fabricating a transistor cell with a high aspect ratio buried

A capacitor of a semiconductor device has a plate electrode which process margin and a method of manufacturing same are disclosed. The plate electrode has a planarized surface and borders a source region. A recessed field oxide layer defining an active region is formed on a semiconductor substrate. Then, an insulating pattern for self-aligning an electrode is formed on the active region. The insulating pattern has a step with respect to the field oxide layer. Thereafter, a trench is formed in the semiconductor substrate by partially removing the field oxide layer, the insulating pattern and a surface portion of the semiconductor substrate. A conductive material is deposited on the semiconductor substrate having the trench and the insulating pattern to form a conductive layer filling the trench. Then, the conductive layer is polished until the insulating pattern is exposed, to thereby obtain an electrode having a planarized surface. The plate electrode does not unnecessarily occupy space of the active region and the plate electrode bordering the active region can be formed by self-alignment with a step between the insulating pattern and the field oxide layer. Therefore, sufficient process margin is provided to generate high yields, and a highly integrated semiconductor device having an AST cell can be realized.

Method of manufacturing trench capacitor with a recessed field oxide

This invention relates to a semiconductor memory device having a cell array and a peripheral circuit and the fabrication method thereof. A semiconductor memory device and the fabrication method are provided wherein source and drain impurity diffusion regions of transistors constituting the cell array have an impurity concentration lower than that of source and drain impurity diffusion regions of transistors constituting the peripheral circuit Thus, the junction's breakdown voltage characteristic of the transistor in the cell array is improved, and the data inverting phenomenon and refresh characteristic deterioration problem due to the leakage current of the transistor in the peripheral circuit area are both solved.

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Kyungki-do, South Korea

Kyu-pil Lee