Intel Corporation

Senju Metal Industry Co., Ltd.

Kyu-Oh Lee

Cheng Xu

Junnan Zhao

Rahul Jain

Sai Vadlamani

Ji Yong Park

Seo Young Kim

Islam A Salama

Yikang Deng

Chong Zhang

Zhimin Wan

Robert L Sankman

Ram S Viswanath

Sri Chaitra Jyotsna Chavali

Ying Wang

Babak Sabi

Srinivas V Pietambaram

Mihir K Roy

Amruthavalli Pallavi Alur

Sheng C Li

Chandra Mohan Jha

Wei-Lun Kane Jen

Shunsaku Yoshikawa

Yongki Min

Amanda E Schuckman

Prithwish Chatterjee

Tsukasa Ohnishi

Ken Tachibana

Jiwei Sun

Hikaru Nomura

Zhenguo Jiang

Yoshie Yamanaka

Zheng Zhou

Lingtao Liu

Chandra Mohan M Jha

Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.

Methods to selectively embed magnetic materials in substrate and corresponding structures

Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.

Substrate assembly with encapsulated magnetic feature

Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

Methods to embed magnetic material as first layer on coreless substrates and corresponding structures

Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.

Methods to pattern TFC and incorporation in the ODI architecture and in any build up layer of organic substrate

An integrated circuit (IC) package comprises a substrate comprising a dielectric and a thermal conduit that is embedded within the dielectric. The thermal conduit has a length that extends laterally within the dielectric from a first end to a second end. An IC die is thermally coupled to the first end of the thermal conduit. The IC die comprises an interconnect that is coupled to the first end of the thermal conduit. An integrated heat spreader comprises a lid over the IC die and at least one sidewall extending from the edge of the lid to the substrate that is thermally coupled to the second end of the thermal conduit.

Effective heat conduction from hotspot to heat spreader through package substrate

An integrated circuit package may be formed having a heat transfer fluid chamber, wherein the heat transfer fluid chamber may be positioned to allow a heat transfer fluid to directly contact an integrated circuit device within the integrated circuit package. In one embodiment, a first surface of the integrated circuit device may be electrically attached to a first substrate. The first substrate may then may be electrically attached to a second substrate, such that the integrated circuit device is between the first substrate and the second substrate. The second substrate may include a cavity, wherein the heat transfer fluid chamber may be formed between a second surface of the integrated circuit device and the cavity of the second substrate. Thus, at least a portion of a second surface of the integrated circuit device is exposed to the heat transfer fluid which flows into the heat transfer fluid chamber.

Thermal management solutions for integrated circuit packages

A package substrate is disclosed. The package substrate includes a substrate core, a cavity below the substrate core that extends from a surface of a first resist layer to a bottom surface of the package substrate, and a first terminal and a second terminal in the first resist layer. The package substrate also includes one or more passive components that are coupled inside the cavity to the first terminal and the second terminal.

Methods for attaching large components in a package substrate for advanced power delivery

A semiconductor device package structure is provided. The semiconductor device package structure includes a substrate having a cavity, and phase change material within the cavity. In an example, the phase change material has a phase change temperature lower than 120 degree centigrade. A die may be coupled to the substrate. In an example, the semiconductor device package structure includes one or more interconnect structures that are to couple the die to the phase change material within the cavity.

Phase change material in substrate cavity

Techniques for fabricating a semiconductor package having magnetic materials embedded therein are described. For one technique, fabrication of package includes: forming a pad and a conductive line on a build-up layer; forming a raised pad structure on the build-up layer, the raised pad comprising a pillar structure on the pad; encapsulating the conductive line and the raised pad structure in a magnetic film comprising one or more magnetic fillers; planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar; depositing a primer layer on the top surfaces; removing one or more portions of the primer layer above the raised pad structure to create an opening; and forming a via in the opening on the raised pad structure. The primer layer may comprise one or more of a build-up layer, a photoimageable dielectric layer, and a metal mask.

Embedding magnetic material, in a cored or coreless semiconductor package

Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.

Semiconductor packages with embedded bridge interconnects

An integrated circuit (IC) structure includes a first IC package (ICP), including a first resist surface provided with a first plurality of conductive contacts (CCs), a first recess including a second resist surface disposed at a bottom of the recess and having a second plurality of CCs, and a second recess, including a third resist surface disposed at a bottom of the recess and provided with a fourth plurality of CCs. The IC structure further includes an IC component with a first surface and a second surface, the second surface having a third plurality of CCs coupled to the second plurality of CCs of the first ICP. The IC structure further includes a second ICP having a first surface and a second surface, with one or more CCs located at the second surface and coupled to at least one of the first plurality of CCs of the first ICP.

Integrated circuit structures with recessed conductive contacts for package on package

Growing community of inventors

Chandler, AZ, United States of America

Kyu-Oh Lee