Samsung Electronics Co., Ltd.

Kyoung-sub Shin

Ji-Soo Kim

Jeong-seok Kim

Gyung-Jin Min

Ji-soo Kim

Wan-jae Park

Tae-hyuk Ahn

Sang-sup Jeong

Jeong-sic Jeon

Won-seok Lee

Sung-choon Lee

Cheon-jin Yun

A semiconductor memory device and manufacturing method, including a bit line connector and a lower electrode connector that respectively connect a bit line and a capacitor lower electrode of the device to active areas of a semiconductor substrate. The connectors are formed using a line-type self-aligned photoresist mask pattern positioned on an interlevel dielectric layer formed on the substrate, which exposes only a portion of the dielectric layer corresponding to a source region and which extends in a direction which a gate electrode extends, to provide a misalignment margin. The bit line connector and the lower electrode connector are respectively formed by one-time mask processes. A contact hole for the bit line connector in a cell area, and a contact hole for a metal wiring plug in a peripheral area are simultaneously formed, alleviating etching burden during subsequent forming of a metal wiring pad.

Semiconductor memory device and method of manufacturing the same

In a method for determining the degree of charge-up induced by plasma used for manufacturing a semiconductor device and an apparatus therefor, a predetermined region on a surface of a wafer on which a plasma process has been performed is repeatedly scanned with a primary electron beam. Secondary electrons generated by a reaction between the primary electron beam and the surface of the wafer that are emitted to the outside of the surface of the wafer are collected. The degree of charge-up induced at the surface of the wafer by the plasma used during the plasma process is determined from the change in the amount of collected secondary electrons. Determination as to whether a contact hole is opened or as to the degree of degradation of a gate insulating layer is made based on the degree of charge-up.

Method of determining whether a conductive layer of a semiconductor device is exposed through a contact hold

In a method of forming a self-aligned contact, gates are formed on a semiconductor substrate in a striped pattern. Bit lines are formed in a striped pattern that extends cross-wise to the gates. The bit lines are isolated from one another by a first interlayer insulation layer. Next, a second interlayer insulation layer is formed between the bit lines, and a photoresist film pattern is formed on the second interlayer insulation layer. The photoresist film pattern is used for forming contact holes extending between the gates down to conductive pads. The contact holes are filled to form conductive plugs that contact the conductive pads. The photoresist film pattern is formed as a series of stripes which extend parallel to the gates. The stripes of photoresist expose segments of the bit lines and the portions of the second interlayer insulation layer disposed directly above the conductive film pads, thereby securing a sufficient alignment margin, and exposing a large underlying area to be etched in forming the contact holes. To form a semiconductor device, a third interlayer insulation layer, an etch stop layer, an oxide layer and a hard mask layer are formed on the conductive plugs. Next, a second photoresist film pattern is formed on the hard mask layer. The hard mask layer and the oxide layer are etched using the second photoresist film pattern as an etching mask until the etch stop layer is exposed. Second contact holes for use in forming capacitor lower electrodes are formed by sequentially removing the exposed etching stop layer and the exposed third interlayer insulation layer using the hard mask layer as an etching mask, until the second contact holes expose the conductive plugs.

Method of forming a self-aligned contact, and method of fabricating a semiconductor device having a self-aligned contact

Method of determining degree of charge-up induced by plasma used for manufacturing semiconductor device and apparatus therefor

Semiconductor memory device with a connector for a lower electrode or a bit line

A method of manufacturing a semiconductor device including various contact studs is provided. According to the method, a plurality of contact holes for various metal contact studs aligned to a bit line, a gate, a semiconductor substrate, or an electrode are formed simultaneously after a capacitor formation process. In this case, an etch stop pattern provided for stopping a selective etching process for forming the contact holes covers the bit line or conductive plugs formed on the semiconductor substrate. The thickness of a first etch stop pattern formed on the bit line or an electrode is similar or substantially the same as a second etch stop pattern formed on conductive plugs. To this end, the method involves selectively removing a capping insulating layer on the bit line for a self aligned contact (SAC) process for forming a conductive pad connected to a capacitor and then depositing a separate etch stop layer. Alternatively, the method may involve reducing the thickness of the capping insulating layer to use it as the first etch stop pattern and forming another second etch stop pattern. In this case, a process of patterning an upper electrode of a capacitor is performed, followed by a process of etching the capping insulating layer.

Method of manufacturing semiconductor memory device including various contact studs

A bit line structure for semiconductor devices, and a fabrication method thereof are provided. In this method, a first conductive film pattern, which fills a first contact hole and is used as a bit line, is formed on a first dielectric film pattern having the first contact hole formed on a semiconductor substrate. A lower part protecting layer pattern, comprised of an anti-reflectance coating (ARC) layer used in a process for patterning the first dielectric layer pattern, is formed on the interface between the first conductive layer pattern and the first dielectric layer pattern. A spacer for covering the sidewall of the first conductive film pattern is formed. An upper part protecting layer pattern comprised of an upper ARC layer is formed to cover the upper part of the first conductive layer pattern. A second dielectric layer pattern having a second contact hole is formed to cover the first conductive layer pattern. A second conductive layer pattern filling the second contact hole is formed and used as a storage node of a capacitor.

Method of fabricating a bit line structure for a semiconductor device

Method of manufacturing a semiconductor memory device

A semiconductor wafer having an active region where the active semiconductor devices are formed and a peripheral region between the active region and the wafer edge, is patterned by forming a patterned photoresist layer on the active region, such that the peripheral region is free of photoresist thereon. The patterned photoresist layer may be formed by forming a photoresist layer on the active region and on the peripheral region of the semiconductor wafer and removing the photoresist layer from the peripheral region of the semiconductor wafer. The photoresist in the active region is patterned. By removing the photoresist layer in the peripheral region of the wafer, excess etchant accumulation at the boundary of the active region and peripheral region is prevented, thereby reducing or preventing pitting of an underlying layer at the boundary.

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Sungnam, South Korea

Kyoung-sub Shin