Samsung Electronics Co., Ltd.

Kyoung-Sub Shin

Myeong-Cheol Kim

Min-Chul Sun

Dong-hyun Kim

Jun-ho Yoon

Hong Seok Cho

Ki-Jeong Kim

Yoo-Chul Kong

Dae-Hyun Jang

Hak-sun Lee

Bum-Soo Kim

Seung-Pil Chung

Je-Woo Han

Jung-Ik Oh

Dae-hyun Jang

Sung-Soo Ahn

Jae-Ho Min

Won-Bong Jung

Jin-Hyuk Yoo

Hyun-Sung Kim

O Ik Kwon

Min-Kyung Yun

Jong-Kyu Kim

Jeong-Dong Choe

Sung-Il Cho

Jeong-yun Lee

Seok-Woo Nam

Yong-Ho Jeon

Byeong-Soo Kim

Gang Zhang

Sung-Sam Lee

Kyung-Yub Jeon

Cheol-Kyu Lee

Yong-Hyun Kwon

Joon-Seok Moon

Ken Tokashiki

Seong-Soo Lee

Yil-hyung Lee

Hyung-yong Kim

Young-kyu Cho

Jong-Soon Park

Kung-Hyon Nam

Jin-Ho Min

In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

Methods of manufacturing semiconductor devices by etching active fins using etching masks and forming source/drain layers on the active fins

Methods of manufacturing semiconductor devices by etching active fins using etching masks

In an example embodiment a method of processing a substrate includes forming a plasma in a plasma chamber and using charged grids to form an ion beam and to thereby accelerate ions from the plasma chamber to a processing chamber. An auxiliary heater, which may be a radiant heater, may be used to pre-heat a grid to a saturation state to accelerate heating and concomitant distortion of the grid. A process recipe may pre-compensate for distortion of the grid.

Method of processing a substrate using an ion beam and apparatus for performing the same

Methods of manufacturing finFET semiconductor devices

Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.

Semiconductor device

A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.

Semiconductor devices

According to example embodiments, a method of fabricating a semiconductor device includes: forming a preliminary stack structure including upper and lower preliminary stack structures by alternately stacking a plurality of interlayer insulating and sacrificial layers on a cell, first pad area, dummy area and second pad area of a substrate; removing an entire portion of the upper preliminary stack structure on the second pad area; forming a first mask defining openings over parts of the first and second pad areas; etching an etch depth corresponding to ones of the plurality of interlayer insulating and sacrificial layers through a remaining part of the preliminary stack structure exposed by the first mask; and repetitively performing a first staircase forming process that includes shrinking sides of the first mask and etching the etch depth through remaining parts of the plurality of interlayer insulating and sacrificial layers exposed by the shrunken first mask.

Method of fabricating semiconductor devices having vertical cells

In a semiconductor device, parallel first and second conductive lines having a unit width extend from a memory cell region into a connection region. A trim region in the connection region includes pads respectively connected to the first and second conductive lines but are separated by a width much greater than the unit width.

Semiconductor device and method forming patterns with spaced pads in trim region

A method of forming micropatterns separated over a misalignment margin includes forming a first mold pattern including a main pattern and a separation-assist pattern, forming a first spacer mask having a first width around the first mold pattern, forming a second mold pattern using the first spacer mask as an etch mask, forming a second spacer mask having a second width around the second mold pattern, and forming a target pattern using the second spacer mask as an etch mask.

Method of forming micropatterns

A memory device includes a plurality of channels, a plurality of first charge storage sites coupled to first sides of respective ones of the channels, and a plurality of second charge storage sites coupled to second sides of respective ones of the channels. The first charge storage sites correspond to first memory cells and the second charge storage sites coupled to second memory cells. At least one of the channels is a dummy channel not connected to a bit line, and a blocking layer is contiguously formed around the first and second charge storage sites and the channels.

Vertical memory devices and methods of manufacturing the same

Provided may be a semiconductor memory device and a method of forming the semiconductor memory device. The memory device of example embodiments may include a bit line structure including a bit line on a semiconductor substrate, and a buried contact plug structure including a buried contact pad and a buried contact plug that extends in a lower portion of the bit line from one side of the bit line and connected to the buried contact pad. A width of the buried contact plug near a top surface of the buried contact pad may be greater than a width of the buried contact plug adjacent to the bit line.

Semiconductor memory device and method of forming the same

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Seongnam-si, South Korea

Kyoung-Sub Shin