Adeia Semiconductor Bonding Technologies Inc.

Kyong-Mo Bang

Belgacem Haba

Zhuowen Sun

Yong Qin Chen

Laura Wills Mirkarimi

Rajesh Katkar

Gabriel Z Guevara

Bongsub Lee

Akash Agrawal

Tu Tam Vu

Xuan Li

Long Huynh

Gaius Gillman Fountain, Jr

Wael Zohni

Teck-Gyu Kang

Ron Zhang

Willmar E Subido

David A Gibson

Young-Gon Kim

John B Riley, Iii

Jae M Park

Thomas Workman

Suhail Jaan Sadiq

A cooling structure having a first side and a second side opposite the first side can be formed through a method comprising, forming an inlet and an outlet in a first substrate, forming at least one channel on the second side of the first substrate, wherein the at least one channel is in fluid communication with the inlet and outlet, forming a plurality of nozzles on the first side of a second substrate, and forming a plurality of channels on the second side of the second substrate opposite the first side of the second substrate. The plurality of channels is aligned with the plurality of nozzles, and the second side of the first substrate is bonded to the first side of the second substrate.

Electronic device cooling structures bonded to semiconductor elements

Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The cold plate has a perimeter sidewall, a top portion and pairs of opposing cavity sidewalls. The perimeter sidewall extends downwardly from the top portion to a backside of the semiconductor device to define a perimeter of the cold plate. Each pair of opposing cavity sidewalls extends downwardly from the top portion towards the backside of the semiconductor device to define a coolant chamber volume therebetween. A distance between each pair of opposing cavity sidewalls in a direction parallel with the backside of the semiconductor device defines a width of a corresponding coolant chamber volume and a spacing between adjacent coolant chamber volumes, wherein the ratio of width to spacing is about 1:1.

Fluid channel geometry optimizations to improve cooling efficiency

A device package comprising an integrated cooling assembly. The integrated cooling assembly comprises a semiconductor device and a cold plate attached to the semiconductor device. The cold plate comprises a top portion and a bottom portion horizontally adjacent to the top portion. The top portion comprises upper cavity dividers extending downwardly to define upper cavity volumes. The bottom portion comprises lower cavity dividers extending upwardly to define lower cavity volumes. The upper cavity dividers and the lower cavity dividers alternate across a horizontal length of the cold plate.

Integrated cooling assemblies for advanced device packaging and methods of manufacturing the same

A microelectronic package includes at least one microelectronic element having a front surface defining a plane, the plane of each microelectronic element parallel to the plane of any other microelectronic element. An encapsulation region overlying edge surfaces of each microelectronic element has first and second major surfaces substantially parallel to the plane of each microelectronic element and peripheral surfaces between the major surfaces. Wire bonds are electrically coupled with one or more first package contacts at the first major surface of the encapsulation region, each wire bond having a portion contacted and surrounded by the encapsulation region. Second package contacts at an interconnect surface being one or more of the second major surface and the peripheral surfaces include portions of the wire bonds at such surface, and/or electrically conductive structure electrically coupled with the wire bonds.

Microelectronic packages having stacked die and wire bond interconnects

A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate. The assembly further includes a second microelectronic package overlying the first microelectronic package and having terminals joined to the stack terminals of the first microelectronic package.

Stackable microelectronic package structures

A microelectronic assembly can include an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and fourth connection regions, and first and second microelectronic packages. The first microelectronic package can include first and second microelectronic elements, and the second microelectronic package can include third and fourth microelectronic elements. Each microelectronic element can be electrically coupled to the address bus via the respective connection region. An electrical characteristic between the first and second connection regions can be within a same tolerance of the electrical characteristic between the second and third connection regions.

High-bandwidth memory application with controlled impedance loading

An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out ('FO') region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.

Wafer-level packaging using wire bond wires in place of a redistribution layer

A microelectronic package can include a substrate having first and second surfaces, first, second, and third microelectronic elements each having a surface facing the first surface, terminals exposed at the second surface, and leads electrically connected between contacts of each microelectronic element and the terminals. The substrate can have first, second, and third spaced-apart apertures having first, second, and third parallel axes extending in directions of the lengths of the apertures. The contacts of the first, second, and third microelectronic elements can be aligned with one of the first, second, or third apertures. The terminals can include first and second sets of first terminals configured to carry address information. The first set can be connected with the first and third microelectronic elements and not with the second microelectronic element, and the second set can be connected with the second microelectronic element and not with the first or third microelectronic elements.

TFD I/O partition for high-speed, high-density applications

Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

Fan-out wafer-level packaging using metal foil lamination

A fan-out microelectronic package is provided in which bond wires electrically couple bond pads on a microelectronic element, e.g., a semiconductor chip which may have additional traces thereon, with contacts at a fan-out area of a dielectric element adjacent an edge surface of the chip. The bond wires mechanically decouple the microelectronic element from the fan-out area, which can make the electrical interconnections less prone to reliability issues due to effects of differential thermal expansion, such as caused by temperature excursions during initial package fabrication, bonding operations or thermal cycling. In addition, mechanical decoupling provided by the bond wires may also remedy other mechanical issues such as shock and possible delamination of package elements.

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Fremont, CA, United States of America

Kyong-Mo Bang