Samsung Electronics Co., Ltd.

Kyomin Sohn

Jaeyoun Youn

Seongil O

Kijun Lee

Sukhan Lee

Sunghye Cho

Myungkyu Lee

Shinhaeng Kang

Nam Sung Kim

Youngcheon Kwon

Namsung Kim

Sang-Hyuk Kwon

Haesuk Lee

Seongmuk Kang

Daehyun Kim

Eunae Lee

Jiho Kim

Hak-Soo Yu

Sanghyuk Kwon

Hweesoo Kim

Suk Han Lee

Hak-soo Yu

Youngmin Kang

Kyung-ho Lee

Jong-Ho Moon

Jongpil Son

Yeonggeol Song

Chisung Oh

Hyongryol Hwang

Ki-Heung Kim

Byeongho Kim

SeungHan Woo

Yong-Ki Kim

Eun Ae Lee

Soojung Rho

Ikjoon Chang

Disclosed is a memory device which includes a plurality of memory banks and control logic. The control logic receives a plurality of column address bits and a plurality of read commands. The control logic includes a processing-in-memory (PIM) address generator. In a first operation mode, the control logic sends the plurality of column address bits to a memory bank. In a second operation mode, when the PIM address generator receives a first read command of the plurality of read commands, the control logic sends, to the memory bank, a first PIM address generated based on remaining column address bits other than some column address bits of the plurality of column address bits.

Memory device, memory module, and operating method of memory device for processing in memory

A memory device includes an ECC circuit that performs error correction code (ECC) encoding on input data to generate write data, and a memory cell array including a plurality of memory cells that stores the write data. The ECC circuit includes a data splitter that splits the input data into first sub-data and second sub-data, a first ECC encoder that performs ECC encoding on the first sub-data to generate first sub-parity data, a second ECC encoder that performs ECC encoding on the second sub-data to generate second sub-parity data, and a data scrambler that performs a data scrambling operation with respect to the first sub-data, the second sub-data, the first sub-parity data, and the second sub-parity data based on a structure of the memory cell array to generate the write data.

Memory device and operation method thereof

A memory system includes a plurality of volatile memory devices and a memory controller. The memory controller causes different amounts of error correction parity information to be generated depending on a request from a host device and depending on failed memory cell counts. The memory controller includes an error correction level (ECL) manager configured to receive cache line data from the host device through the host interface, and output an error correction code (ECC) control signal indicating one of a first correction level and a second correction level. The correction levels are based on cell reliability information and data reliability request information. The data reliability request information is associated with the cache line data. An ECC engine generates first parity symbols associated with the cache line data, and may, depending on the ECC control signal, generate additional parity symbols.

Memory system, method of operating the same, and electronic system including the same

A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.

Memory device including processing circuit, and electronic device including system on chip and memory device

A memory device for reducing timing parameters and power consumption for an internal processing operation and a method of implementing the same are provided. The memory device includes a memory cell array, a processing-in-memory (PIM) circuit configured to perform a processing operation and a control logic circuit configured to control a normal mode and an internal processing mode. The control logic circuit writes an operation result obtained by the processing operation of the PIM circuit in the internal processing mode in the memory cell array and provides read data read from the memory cell array to the PIM circuit.

Memory device for reducing timing parameters and power consumption for internal processing operation and method of implementing the same

A memory device which includes a plurality of memory chips. Each of the plurality of memory chips includes a plurality of memory banks and a logic circuit performing a read operation on data stored in the plurality of memory banks based on a first command and a first address received from a host. When a PIM instruction set is stored before the first command and the first address are received, the logic circuit is configured to perform a PIM command execution operation. When an error associated with the PIM command execution operation occurs, the logic circuit is configured to generate error data and record the error data at the log register through the first channels. The logic circuit is configured to output event data indicating an existence of the error data to the host in a first operation mode. The logic circuit is configured to output the error data to the host in a second operation mode.

Memory devices and electronic devices outputting event data related to occurrences of errors and operating methods of memory devices

A memory device includes a memory cell array and an error correction code (ECC) circuit. The ECC circuit, which is configured to correct an error in a data code read out from the memory cell array, includes: (i) a syndrome calculating unit configured to operate a plurality of syndromes based on the data code and an H-matrix, (ii) an error location detecting unit configured to generate an error vector based on the plurality of syndromes, and (iii) an error correcting unit configured to correct an error within the data code based on the error vector, and output corrected data.

Error correction code circuit, memory device including error correction code circuit, and operation method of error correction code

A memory device includes a memory cell array having a plurality of rows of memory cells therein, and a row hammer managing circuit, which is configured to detect a row hammer address based on a pre row hammer address, and each of a plurality of input row addresses associated with a plurality of accesses during a monitoring period for monitoring the plurality of accesses to a plurality of the rows of memory cells. A refresh control circuit is provided and is configured to perform a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to the row hammer address.

Memory devices and methods thereof for managing row hammer events therein

A semiconductor memory device includes a memory cell array with a plurality of rows of memory cells therein, and a row hammer management (RHM) circuit including a hammer address queue. The RHM circuit is configured to: (i) receive first access row addresses from an external memory controller during a reference time interval, (ii) store a first row address randomly selected from the first access row addresses and second row addresses consecutively received from the memory controller after selecting the first row address, in the hammer address queue as candidate hammer addresses, and (iii) sequentially output the candidate hammer addresses as a hammer address. A refresh control circuit is provided to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows, which are physically adjacent to a memory cell row corresponding to the hammer address.

Integrated circuit memory devices having efficient row hammer management and memory systems including the same

A memory controller to control a memory module including a plurality of data chips, a first parity chip and a second parity chip, includes a system error correction code (ECC) engine and a processor to control the system ECC engine. The system ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder selects one of a plurality of ECC decoding schemes based on decoding status flags and corrects a plurality of symbol errors in a read codeword set from the memory module by performing an ECC decoding on the read codeword set based on the selected decoding scheme and the parity check matrix. The decoding status flags are provided from the plurality of data chips and each of the decoding status flags indicates whether at least one error bit is detected in respective one of the plurality of data chips.

Memory controllers and memory systems including the same

Disclosed is a semiconductor memory device and a memory system, including at least one high-bandwidth memory device configured to store data or output stored data according to an access command, a processor configured to generate the access command for the high-bandwidth memory device, and a logic die on the high-bandwidth memory device and including a last level cache providing a cache function to the processor. The last level cache is configured to perform a cache bypassing operation to directly access the high-bandwidth memory device without a cache replacement operation when an invalid line and a clean line do not exist in a cache miss state in response to a cache read or cache write request by the processor.

Memory system performing cache bypassing operation and cache management method thereof

A storage circuit includes a multi-stage latch circuit having first to fourth transistor pairs therein, which respectively include a pull-up transistor and a pull-down transistor connected in series through a corresponding one of first to fourth storage nodes. An access circuit is provided, which has a plurality of access transistors of different conductivity type therein. The access transistors are electrically coupled to at least two of the first to fourth storage nodes and configured to enable writing of data bits into at least some of the first to fourth storage nodes, and reading of data bits from at least some of the first to fourth storage nodes. A control circuit is provided, which controls the access circuit during the writing and reading.

Latch-based storage circuits having efficient integrated circuit layouts

A memory device may include counters respectively corresponding to rows and each configured to count a number of accesses to a corresponding row, a refresh control circuit, a queue, and first flags respectively corresponding to the rows. The refresh control circuit may change a second flag set in a refresh period every refresh period, and determine whether to put an incoming row address into the queue based on a count value of a counter corresponding to a target row indicated by the incoming row address among the counters, a first flag value of a first flag corresponding to the target row among the first flags, and a second flag value of the second flag set in a current refresh period.

Memory device and refresh method thereof

A memory device supporting a processing-in-memory (PIM) protocol includes a mode register set (MRS) configured to store a first parameter code and a second parameter code regarding the PIM protocol in a first register and a second register, respectively. The first parameter code includes a PIM protocol change code indicating whether a PIM protocol change related to an old version PIM protocol is supported, and the second parameter code includes a PIM protocol code for setting a current operation PIM protocol from among a plurality of PIM protocols. The memory device further includes a PIM circuit configured to perform an internal processing operation based on the current operation PIM protocol.

Backward compatible processing-in-memory (PIM) protocol

A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.

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Yongin-si, South Korea

Kyomin Sohn