Samsung Electronics Co., Ltd.

Kyeong-Han Lee

Young-Joon Choi

Seok-Cheon Kwon

Dong-Yang Lee

Jong-Hwa Kim

In-Young Kim

Yeon-Ho Kim

Dae-Seok Byeon

June Hyung Lee

Sung-soo Lee

Sung-Soo Lee

Seok-cheon Kwon

A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

Flash memory device for outputing data in synch with a first signal in an SDR mode and a DDR mode and a flash memory system including the same

Nonvolatile memory device including a peripheral circuit to receive an address in synch with one of a rising and falling edge of a signal regardless of whether a first or second alignment type is selected and nonvolatile memory system including the same

Flash memory device and flash memory system including the same

A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode.

Flash memory devices with high data transmission rates and memory systems including such flash memory devices

A data output buffer switches it operating mode according to its operating frequency. The data output buffer includes a delay control unit, and a buffer unit. The buffer unit provides data of an internal buffer input line to an external buffer output line. The delay control unit generates a buffer enable signal corresponding to a received reference control signal. The buffer unit blocks the provision of the data to the buffer output line in response to a deactivation of the buffer enable signal. The buffer enable signal remains in an activated state when the period of the reference control signal is shorter than a reference period. The data output buffer may be included in a semiconductor memory device.

Data output buffer whose mode switches according to operation frequency and semiconductor memory device having the same

A nonvolatile semiconductor memory device compensates for temperature changes by holding constant a bit line precharge level. A memory device according to the present invention may include an electrically programmable memory cell array connected to a plurality of word lines and a plurality of bit lines, a bit line voltage supplying circuit for supplying a bit line voltage to the bit lines, a shut-off circuit connecting the memory cell array and the bit line voltage supplying circuit, and a shut-off controlling circuit for controlling the shut off circuit. The shut-off controlling circuit may be constructed to compensate for temperature changes in order to hold the bit-line precharge level constant.

Temperature compensated bit-line precharge

In a non-volatile semiconductor memory device which differentially uses a start programming voltage during a programming operation mode in order to reduce a dispersion for the number of programming loops, the programming method includes previously storing a row address that indicates at least one specific word line among a plurality of word lines; and applying a start programming voltage to the specific word line, when a row address applied in a programming operation mode coincides with the stored row address, the start programming voltage having a level that is different from a level of start programming voltage to be applied to the rest word lines except the specific word line, whereby reducing dispersion for the programming loop number and realizing a high-speed programming operation and operating efficiency.

Non-volatile semiconductor memory device using differential start programming voltage and programming method thereof

Embodiments of the invention provide a power-on reset function that establishes logic circuits in a memory chip at an initial stable state and a power-on read function that triggers a read operation of the memory chip. A first voltage detector output signal transitions when a power supply voltage reaches a first voltage, setting the logic circuits at the initial stable state. A second voltage detector output signal transitions when the power supply voltage reaches a second voltage, placing a latch in a set state that results in activation of a power-on read signal. A power-on read operation is carried out according to the activation of the power-on read signal. If the power supply voltage is not lowered below the first voltage, the second voltage detector output signal does not transition. Accordingly, embodiments are capable of preventing power-on read operations that are unnecessarily performed owing to power noise.

Power detecting circuit and method for stable power-on reading of flash memory device using the same

A flash memory device including a memory cell array block including a plurality of flash memory cells. A program verify voltage generating unit variably generates a program verify voltage that verifies flash memory cells programming. A wordline level selecting unit transfers the program verify voltage to the flash memory cells. And a page buffer, including a latch, stores flash memory cell data and resets the latch whenever the program verify voltage is lowered.

Growing community of inventors

Gyeonggi-do, South Korea

Kyeong-Han Lee