Lucent Technologies Inc.

Agere Systems Inc.

Agere Systems Guardian Corp.

Kwok K Ng

Clifford Alan King

Michel Ranjit Frei

Ya-Hong Xie

Jeff Devin Bude

Peide Ye

Bin Yang

Yi Ma

William Thomas Cochran

Marco Mastrapasqua

Shahriar Moinian

Nathan R Belk

Mark Richard Pinto

Harry T Weston

David Clayton Goldthorp

A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel. The overlapping gate/field plate or p-type pocket extend into the drift region of the device, controlling the electrical potential of the device in a manner that provides the desired control of the electrical potential in the drift region.

III-V power field effect transistors

A heterojunction bipolar transistor includes an emitter or collector region of doped silicon, a base region including silicon-germanium, and a spacer. The emitter or collector region form a heterojunction with the base region. The spacer is positioned to electrically insulate the emitter or collector region from an external region. The spacer includes a silicon dioxide layer physically interposed between the emitter or collector region and the remainder of the spacer.

Heterojunction bipolar transistor

An integrated circuit with a buried layer for increasing the Q of an inductor formed in the integrated circuit. The substrate includes a highly doped buried preserving device and latchup characteristics. The inductor may also include an increased thickness conductive layer in the inductor to further increase Q. The present invention is also directed to a low loss interconnect.

Inductor or low loss interconnect and a method of manufacturing an inductor or low loss interconnect in an integrated circuit

A process for device fabrication in which amorphous silicon is deposited into a narrow gap is disclosed. The gap is an opening between two layers of material. The gap results when a window is formed in one of the two layers and a portion of a third layer at the base of the window is removed. In the formation of a bipolar device, a layer of oxide is formed on a silicon substrate and a layer of silicon is formed on the oxide layer which serves as the extrinsic base for the device. In the bipolar device, a window is formed in the polysilicon and the oxide layer at the base of the window is then removed. In the bipolar device, the silicon substrate underlies the gap and the extrinsic base silicon overlies the gap. When the oxide is removed from the base of the window, a portion of the oxide layer underlying the extrinsic base silicon is removed as well, thereby forming a gap between the extrinsic base silicon and the underlying silicon substrate. In the process of the present invention, the resulting gap has a proximate end which is the opening of the gap into a window and a distal end which is the interface between the gap and the remaining oxide. The width of the gap is less than about 20 nm. The gap is then subjected to conditions that cause the gap to have a first height at its proximate end which is greater than its height at its distal end. The tapered gap is then filled with polysilicon. Because of its tapered configuration, the polysilicon uniformly fills the gap, without significant voids therein.

Process for fabricating bipolar and BiCMOS devices

A device with at least one noise-sensitive element, at least one noise-generating element, and a porous silicon barrier in the substrate is disclosed. The porous silicon barrier isolates the noise-sensitive element from the signals coupled into the substrate by the noise-generating element. A process for making this device is also disclosed.

Integrated circuit device with isolated circuit elements

Growing community of inventors

Warren, NJ, United States of America

Kwok K Ng