Samsung Electronics Co., Ltd.

Kwang-soo Seol

Sang-jin Park

Sang-Moo Choi

Sung-il Park

Jong-seob Kim

Sung-hoon Lee

Sang-min Shin

Eun-ha Lee

Jung-hun Sung

Woong-chul Shin

Yoon-Dong Park

In-Jun Hwang

Kyung-sang Cho

Ju-hee Park

Jong-bong Park

Min-ho Yang

Jung-Dal Choi

Jae-young Choi

Jae-Ho Lee

Sun-ae Seo

Myoung-jae Lee

Ki-Hwan Choi

Jae-woong Hyun

Byung-Ki Kim

Yo-sep Min

Jae-Sung Sim

Shin-Ae Jun

Seung-Hyun Moon

Young-Kwan Cha

Eun-joo Jang

Hion-suck Baik

Jung-eun Lim

Hlon-suck Baik

Provided is a method of operating a nonvolatile memory device to perform a programming operation or an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and an AC perturbation pulse to the nonvolatile memory device to perform the programming operation or the erase operation.

Method of operating nonvolatile memory device

Crystalline aluminum oxide layers having increased energy band gap, charge trap memory devices including crystalline aluminum oxide layers and methods of manufacturing the same are provided. A method of forming an aluminum oxide layer having an increased energy band gap includes forming an amorphous aluminum oxide layer on a lower film, introducing hydrogen (H) or hydroxyl group (OH) into the amorphous aluminum oxide layer, and crystallizing the amorphous aluminum oxide layer including the H or OH.

Crystalline aluminum oxide layers having increased energy band gap, charge trap layer devices including crystalline aluminum oxide layers, and methods of manufacturing the same

Provided is an aluminum (Al) doped charge trap layer, a non-volatile memory device and methods of fabricating the same. The charge trap layer may include a plurality of silicon nano dots that trap charges and a silicon oxide layer that covers the silicon nano dots, wherein the charge trap layer is doped with aluminum (Al). The non-volatile memory device may include a substrate including a source and a drain on separate regions of the substrate, a tunneling film on the substrate contacting the source and the drain, the charge trap layer according to example embodiments, a blocking film on the charge trap layer, and a gate electrode on the blocking film.

Al-doped charge trap layer and non-volatile memory device including the same

Provided is an image sensor including a sensing transistor having two gates and a method of operating the image sensor. The image sensor may include a photoelectric conversion device, a sensing transistor which may have a first gate connected to a floating diffusion region in which charges generated from the photoelectric conversion region are stored and a second gate separated from the first gate, a reset transistor that may be connected to the floating diffusion region and may reset a potential of the floating diffusion region, a control voltage source that may supply a control applied to the second gate, and a column output line which may be connected to a source of the sensing transistor.

Image sensor with sensing transistor having two gates and method of operating the same

Provided is a method of forming an aluminum oxide layer and a method of manufacturing a charge trap memory device using the same. The method of forming an aluminum oxide layer may include forming an amorphous aluminum oxide layer on an underlying layer, forming a crystalline auxiliary layer on the amorphous aluminum oxide layer, and crystallizing the amorphous aluminum oxide layer. Forming the crystalline auxiliary layer may include forming an amorphous auxiliary layer on the amorphous aluminum oxide layer; and crystallizing the amorphous auxiliary layer.

Method of forming aluminum oxide layer and method of manufacturing charge trap memory device using the same

Provided is a method of operating a nonvolatile memory device to perform an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and a DC perturbation pulse to the nonvolatile memory device to perform the erase operation.

A method of programming a memory device may include applying a program voltage to a memory cell of the memory device and consecutively applying a plurality of verifying voltages to the memory cell. The verifying voltages may be consecutively applied with a same voltage magnitude after applying the program voltage. The verifying voltages may be consecutively applied with sequentially decreasing magnitudes after applying the program voltage.

Method of programming memory device

A nonvolatile memory device including a nano dot and a method of fabricating the same are provided. The nonvolatile memory device may include a lower electrode, an oxide layer on the lower electrode, a nano dot in the oxide layer and an upper electrode on the oxide layer. In example embodiments, the current paths inside the oxide layer may be unified, thereby stabilizing the reset current.

Nonvolatile memory device including nano dot and method of fabricating the same

A non-volatile memory cell programming method of programming 2-bit data in a memory cell having 4 threshold voltage distributions may include a first program operation of programming a first bit of the 2-bit data in the memory cell by applying a first programming voltage to the memory cell; a second program operation of programming a second bit of the 2-bit data in the memory cell by applying a second programming voltage to the memory cell; and a stabilization operation of applying a stabilization voltage having an electric field opposite in polarity to an electric field formed by the first and second programming voltages to the memory cell after one of the first and second program operations that corresponds to a higher one of the first and second programming voltages is performed.

Non-volatile memory cell programming method

Al-doped charge trap layer, non-volatile memory device and methods of fabricating the same

Provided are a charge trap semiconductor memory device including a charge trap layer on a semiconductor substrate, and a method of manufacturing the charge trap semiconductor memory device. The method includes: (a) coating a first precursor material on a surface of a semiconductor substrate to be deposited and oxidizing the first precursor material to form a first layer formed of an insulating material; (b) coating a second precursor material formed of metallicity on the first layer; (c) supplying the first precursor material on the surface coated with the second precursor material to substitute the second precursor material with the first precursor material; and (d) oxidizing the first and second precursor materials obtained in (c) to form a second layer formed of an insulating material and a metal impurity, and (a) through (d) are performed at least one time to form a charge trap layer having a structure in which the metal impurity is isolated in the insulating material.

Charge trap layer for a charge trap semiconductor memory device and method of manufacturing the same

A semiconductor memory device may include a semiconductor substrate, at least one control gate electrode, at least one storage node layer, at least one tunneling insulating layer, at least one blocking insulating layer, and/or first and second channel regions. The at least one control gate electrode may be recessed into the semiconductor substrate. The at least one storage node layer may be between a sidewall of the at least one control gate electrode and the semiconductor substrate. The at least one tunneling insulating layer may be between the at least one storage node layer and the at least one control gate electrode. The at least one blocking insulating layer may be between the storage node layer and the control gate electrode. The first and second channel regions may be between the at least one tunneling insulating layer and the semiconductor substrate to surround at least a portion of the sidewall of the control gate electrode and/or may be separated from each other.

Semiconductor memory device including recessed control gate electrode

A semiconductor memory device may include a semiconductor substrate, a control gate electrode recessed in the semiconductor substrate, a storage node layer between the control gate electrode and the semiconductor substrate, a tunneling insulating layer between the storage node layer and the semiconductor substrate, a blocking insulating layer between the storage node layer and the control gate electrode, and first and second channel regions surrounding the control gate electrode and separated by a pair of opposing separating insulating layers. A method of operating the semiconductor memory device may include programming data in the storage node layer by charge tunneling through the blocking insulating layer, thus achieving relatively high reliability and efficiency.

Method of operating a semiconductor memory device having a recessed control gate electrode

Non-volatile memory devices and methods of programming a non-volatile memory device in which electrons are moved between charge trap layers through a pad oxide layer are provided. The non-volatile memory devices include a charge trap layer on a semiconductor substrate and storing electrons, a pad oxide layer on the first charge trap layer, and a second trap layer on the pad oxide layer and storing electrons. In a programming mode in which data is written, the stored electrons are moved between a first position of the first charge trap layer and a first position of the second charge trap layer through the pad oxide layer or between a second position of the first charge trap layer and a second position of the second charge trap layer through the pad oxide layer.

Growing community of inventors

Suwon-si, South Korea

Kwang-soo Seol