Freescale Semiconductor,inc.

Motorola Corporation

Advanced Micro Devices Corporation

Nxp Usa, Inc.

Amd Inc.

Semiconductor Research Corporation

Kurt H Junker

Mark Douglas Hall

Marilyn I Wright

Kyle W Patterson

Tab Allen Stephens

Paul Grudowski

Gregory S Spencer

Douglas M Reber

Edward K Theiss

Srikanteswara Dakshiina-Murthy

Dean J Denning

Tien Ying Luo

Gerald A Martin

Thomas J Kropewnicki

Mehul D Shroff

Srikanteswara Dakshina-Murthy

Marius K Orlowski

Suresh Venkatesan

Peter L G Ventzek

Michael D Turner

Venkat Kolagunta

Tu-Anh N Tran

Dina H Triyoso

Ritwik Chatterjee

John G Ekerdt

Andrew G Nagy

Phillip E Crabtree

Tien-Ying Luo

Xiangzheng Bo

Jin Miao Shen

Edward Raymond Engbrecht

Nicole R Grove

Marijean E Azrak

Brian J Fisher

Vikas R Sheth

Yang-Ming Sun

Jason A Vires

Philip E Crabtree

Xiang-Zheng Bo

A method for forming a semiconductor structure includes forming a bond pad over a last metal layer of the semiconductor structure wherein the bond pad includes a wire bond region; and recessing the wire bond region such that the wire bond region has a first thickness and a region of the bond pad outside the wire bond region has a second thickness that is greater than the first thickness.

Methods for forming semiconductor devices with stepped bond pads

A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.

Method of making a die with recessed aluminum die pads

In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS layer is over an organic anti-reflective coating (ARC) that is over the conductive layer. The low temperature TEOS layer provides adhesion between the organic ARC and the photoresist, has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC, to reduce undesired reflection.

Semiconductor device having an organic anti-reflective coating (ARC) and method therefor

A method for forming a TSV layout reduces recessing in a silicon nitride layer caused by forming the TSV through a silicon nitride layer having an intrinsic tensile stress or neutral stress. In one embodiment, the method includes compensating for the tensile stressed silicon nitride layer by either moving the TSV location to an area of intrinsic tensile stress, or by substituting a compressively stressed silicon nitride layer in the area of the TSV. The compressively stressed silicon nitride layer experiences less recessing during a TSV etch process than a silicon nitride layer under tensile stress. The smaller recesses are more readily filled when a dielectric liner is applied to the sidewalls of the TSV, reducing the possibility of voids being formed. Also, the smaller recesses require smaller exclusion zones, resulting in less surface area of an integrated circuit being used for the TSVs, as well as greater reliability and improved yields.

Method for forming a through silicon via layout

A method of forming a semiconductor device includes forming a high dielectric constant material over a semiconductor substrate, forming a conductive material over the high dielectric constant material, and performing an anneal in a non-oxidizing ambient using ultraviolet radiation to remove defects in the high dielectric constant material. Examples of a non-oxidizing ambient include for example nitrogen, deuterium, a deuterated forming gas (N/D), helium, argon or a combination of any two or more of these. Additional anneals using ultraviolet radiation may be performed. These additional anneals may occur in non-oxidizing or oxidizing ambients.

Method of removing defects from a dielectric material in a semiconductor

A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate () and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer () of a first stressor material over the semiconductor structure, said first stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer () of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.

Multilayer silicon nitride deposition for a semiconductor device

A method for imparting stress to the channel region of a transistor is provided. In accordance with the method, a semiconductor layer () is provided which has a dielectric layer () disposed beneath it. A trench () is created which extends through the semiconductor layer and into the dielectric layer, and the trench is backfilled with a stressor material (), thereby forming a trench isolation structure. A channel region () is defined in the semiconductor layer adjacent to the trench isolation structure.

Deep STI trench and SOI undercut enabling STI oxide stressor

A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile.

Method of forming a semiconductor device with multiple tensile stressor layers

A method for making a semiconductor device is provided, comprising (a) providing a semiconductor structure comprising a first gate electrode (); (b) forming a first set of organic spacers () adjacent to said first electrode; (c) depositing a first photo mask () over the structure; and (d) simultaneously removing the first set of organic spacers and the first photo mask.

Disposable organic spacers

A method for forming a dielectric layer is disclosed herein. In accordance with the method, a first material is provided () which comprises a suspension of nanoparticles in a liquid medium. A dielectric layer is then formed () on the substrate from the suspension through an evaporative process.

Deposition and patterning of boron nitride nanotube ILD

A method for forming a semiconductor device () includes forming an organic anti-reflective coating (OARC) layer () over the semiconductor device (). A tetra-ethyl-ortho-silicate (TEOS) layer () is formed over the OARC layer (). The TEOS layer () is exposed to oxygen-based plasma at a temperature of at most about 300 degrees Celsius. In an alternative embodiment, the TEOS layer () is first exposed to a nitrogen-based plasma before being exposed to the oxygen-based plasma. A photoresist layer () is formed over the TEOS layer () and patterned. By applying oxygen based plasma and nitrogen based plasma to the TEOS layer () before applying photoresist, pattern defects are reduced.

Plasma treatment for surface of semiconductor device

The present invention includes methods for forming a boron carbo-nitride layer. Additional embodiments include thermal chemical vapor deposition methods for forming a boron carbo-nitride layer. Also integrated circuit devices with a boron carbo-nitride layer are disclosed.

Methods of forming boron carbo-nitride layers for integrated circuit devices

In the fabrication of semiconductor devices using the PECVD process to deposit hardmask material such as amorphous carbon, structure and process are described for reducing migration of species from the amorphous carbon which can damage an overlying photoresist. In one embodiment useful to 248 nm and 193 nm photolithography exposure wavelengths, amorphous carbon is plasma-deposited on a substrate to pre-defined thickness and pre-defined optical properties. A SiON layer is combined with a silicon-rich oxide layer, a silicon-rich nitride layer or a TEOS layer to create a capping layer resistant to species-migration. Layers are formulated to pre-determined thicknesses, refractive indices and extinction coefficients. The capping stacks constitute an effective etch mask for the amorphous carbon; and the hardmask properties of the amorphous carbon are not compromised. The disclosure has immediate application to fabricating polysilicon gates.

Capping layer for reducing amorphous carbon contamination of photoresist in semiconductor device manufacture; and process for making same

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Austin, TX, United States of America

Kurt H Junker