Taiwan Semiconductor Manufacturing Comp. Ltd.

Kuo-Yin Lin

Teng-Chun Tsai

Shen-Nan Lee

Chang-Sheng Lin

Wen-Kuei Liu

Yu-Wei Chou

Kuo-Cheng Lien

Yung-Cheng Lu

Wan-Chun Pan

Hsiang-Pi Chang

Chi-Yuan Chen

Po-Yu Lin

Chia-Shiung Tsai

Chih-Chang Hung

Kuo-Cheng Ching

Huicheng Chang

Li-Ting Wang

Cheng-Tung Lin

Hsin-Hsien Lu

Chih-Ta Wu

Ching-Hong Jiang

Te-Chien Hou

Ming-Liang Yen

Cary Chia-Chiung Lo

Ming-Shiuan She

Yen-Yu Chen

Shi Ning Ju

Chung-Yi Yu

Hongfa Luan

Tsung-Hsun Huang

Chih-I Peng

Pin-Chuan Su

Chih-Hao Wang

Ching-Wei Tsai

Yeur-Luen Tu

Hsing-Lien Lin

Chun-Hsiung Lin

Lan-Lin Chao

Shih-Chi Fu

Feng-Jia Shiu

Ming-Chyi Liu

Yuan-Hung Liu

Ching-Sen Kuo

Jieh-Jang Chen

Chih-Yuan Yang

Kun-Tai Wu

Chi-Yuan Chang

Li-Lan Wu

An apparatus for performing chemical mechanical polish on a wafer includes a polishing head that includes a retaining ring. The polishing head is configured to hold the wafer in the retaining ring. The retaining ring includes a first ring having a first hardness, and a second ring encircled by the first ring, wherein the second ring has a second hardness smaller than the first hardness.

CMP polishing head design for improving removal rate uniformity

A slurry solution for a Chemical Mechanical Polishing (CMP) process includes a wetting agent, a stripper additive that comprises at least one of: N-methyl-2-pyrrolidone (NMP), dimethyl sulfoxide (DMSO), sulfolane, and dimethylformamide (DMF), and an oxidizer additive comprising at least one of: hydrogen peroxide (HO), ammonium persulfate ((NH)SO), peroxymonosulfuric acid (HSO), ozone (O) in de-ionized water, and sulfuric acid (HSO).

CMP slurry solution for hardened fluid material

A method includes following steps. A semiconductor substrate is etched to form semiconductor fins. A dielectric material is deposited into a trench between the semiconductor fins. The semiconductor fins are etched such that top ends of the semiconductor fins are lower than a top surface of the dielectric material. After etching the semiconductor fins, epitaxially growing epitaxial fins on the semiconductor fins, respectively. A chemical mechanical polish (CMP) process is performed on the epitaxial fins, followed by cleaning the epitaxial fins using a non-contact-type cleaning device. The dielectric material is then such that the top surface of the dielectric material is lower than top ends of the epitaxial fins. A gate structure is formed across the epitaxial fins.

Method for manufacturing a FinFET device

A method of manufacturing an integrated circuit device is provided. A first feature, which has a first susceptibility to damage by chemical mechanical processing (CMP), is formed at a first height as measured from an upper surface of the substrate. A second feature, which has a second susceptibility to damage by the CMP, is formed at a second height as measured from the upper surface of the substrate and is laterally spaced from the first feature by a recess. The second height is greater than the first height, and the second susceptibility is less than the first susceptibility. A sacrificial coating is formed in the recess over an uppermost surface of the first feature. CMP is performed to remove a first portion of the sacrificial coating and expose an upper surface of the second feature while leaving a second portion of the sacrificial coating in place over the first feature.

CMP-friendly coatings for planar recessing or removing of variable-height layers

A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.

Method and structure for FinFET devices

A method for manufacturing a semiconductor device is provided. In the method for manufacturing a semiconductor device, at first, a semiconductor substrate of a wafer is etched to form at least one fin. Then, an insulation structure is formed around the fin. Thereafter, the fin is recessed. Then, an epitaxial channel structure is epitaxially grown over the recessed fin. Thereafter, a portion of the epitaxial channel structure over a top surface of the insulation structure is removed. Then, a non-contact-type cleaning operation is performed to clean a top surface of the wafer after removing said portion of the epitaxial channel structure. Thereafter, the top surface of the wafer is cleaned using hydrogen fluoride after removing said portion of the epitaxial channel structure. Then, the insulation structure is recessed, such that the epitaxial channel structure protrudes from the recessed insulation structure.

A chemical mechanical polishing (CMP) chamber is disclosed. The CMP chamber includes a chamber body, a door mounted on the chamber body and a chamber substructure being one selected from a group consisting of a moisture separator separating a moisture generated in the CMP chamber, a supplementary exhaust port, a transparent window mounted on the door, a sampling port mounted on the door, a sealing material including a metal frame, an o-ring for sealing the door and a combination thereof.

System and method for operating chemical mechanical polishing process

Among other things, one or more techniques and/or systems are provided for cleaning a polishing module of a semiconductor polishing apparatus. Purge air flow can be supplied into the polishing module (e.g., directed towards a polishing unit, a shield, and/or other polishing components) to create turbulence air flow within the polishing module. An auxiliary exhaust can be invoked to exhaust one or more particulates removed from the polishing module by the turbulence air flow. A purge air flow cycle can be performed by cycling the purge air flow and the auxiliary exhaust between on and off states. One or more purge air flow cycles can be performed during a main air flow cycle where laminar air flow is supplied into the polishing module and exhausted using a main exhaust. In this way, one or more particulates can be cleaned from the polishing module.

Air purge cleaning for semiconductor polishing apparatus

Some embodiments are directed to a wafer polishing tool. The wafer polishing tool includes a first polisher, a second polisher downstream of the first polisher, a third polisher downstream of the second polisher, and a fourth polisher downstream of the third polisher. The first polisher receives a wafer having a front side and a back side with integrated circuit component devices disposed on the front side of the wafer, and polishes a center region on the back side of the wafer. The second polisher receives the wafer via transporting equipment and buffs the center region of the back side of the wafer. The third polisher receives the wafer via the transporting equipment and polishes a back side edge region of the wafer. The fourth polisher receives the wafer via the transporting equipment and buffs the back side edge region of the wafer.

Wafer back-side polishing system and method for integrated circuit device manufacturing processes

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Jhubei, Taiwan

Kuo-Yin Lin