Sitronix Technology Corporation

Kuo-Wei Tseng

Po-Chi Chen

Jui-Hsuan Cheng

Ying-Chen Chang

A chip packaging structure includes a chip and a film substrate. The chip is formed with a gold bump, and the film substrate is formed with an inner lead, wherein the gold bump includes a first bonding surface and a plurality of side walls. The gold bump is electrically connected to the inner lead through a eutectic material coverage layer, and the first bonding surface and at least one of the plurality of side walls are covered by the eutectic material coverage layer.

Chip packaging structure and related inner lead bonding method

The present invention provides a test pad structure of chip, which comprises a plurality of first internal test pads, a plurality of second internal test pads, a plurality of first extended test pads, and a plurality of second extended test pads. The first internal test pads and the second internal test pads are disposed in a chip. The second internal test pads and the first internal test pads are spaced by a distance. The first extended test pads are connected with the first internal test pads. The second extended test pads are connected with the second internal test pads. The first extended test pads and the second extended test pads may increase the contact area to be contacted by probes. Signals or power are transmitted to the first internal test pads and the second internal test pads via the first extended test pads and the second extended test pads for the probes to test the chip.

Test pad structure of chip

The present invention discloses a lead structure of the circuit, which comprises a first lead and a second lead. The first lead includes a first bump connecting part and a first lead segment. The first lead segment is connected to the first bump connecting part. The width of the first lead segment is smaller than the width of the first bump connecting part. The second lead is adjacent to the first lead and there is a lead gap therebetween. The second lead also includes a second bump connecting part and a first lead segment. The first lead segment of the second lead is connected to the second bump connecting part. The second bump connecting part and the first bump connecting part are arranged staggeredly. The second bump connecting part is adjacent to the first lead segment of the first lead.

Lead structure of circuit with increased gaps between adjacent leads

The present invention provides a manufacturing method for an electronic element of an electronic apparatus. The electronic element includes a substrate, a bump and at least one under bump metal (UBM) layer. The manufacturing method includes sequentially disposing the UBM layer and the bump onto the substrate; and processing an etching operation at the UBM layer to form a breach structure.

Manufacturing method for electronic element

An electronic element for an electronic apparatus includes a substrate; a bump, disposed on the substrate for electrically connecting the electronic apparatus; and at least one under bump metal layer, disposed between the bump and the substrate for the bump to be attached to the substrate; wherein the UBM layer forms a breach structure.

Growing community of inventors

Hsinchu County, Taiwan

Kuo-Wei Tseng