Industrial Technology Research Institute

Au Optronics Corporation

Chunghwa Picture Tubes, Ltd.

Hannstar Display Corporation

Taiwan Tft Lcd Association

Chi Mei Optoelectronics Corporation

Innolux Corporation

Tpo Dispalys Corp.

Win-house Electronic Co., Ltd.

Kuo-Shu Kao

Tao-Chih Chang

Po-Kai Chiu

Tai-Jyun Yu

Yen-Ting Lin

Jing-Yao Chang

Wen-Chih Chen

Wei-Kuo Han

Hsin-Han Lin

Ngai Tsang

Sheng-Tsai Wu

Fang-Jun Leu

Yuan-Cheng Huang

Ji-Yuan Syu

Han-Lin Wu

Yu-Min Lin

Chih-Ming Shen

Chih-Ming Tzeng

Yuan-Yin Lo

I-Hung Chiang

Hsiao-Ming Chang

Tai-Kuang Lee

Power module

A power semiconductor device, including a terminal base, is provided. The terminal base has a first end and a second end opposite to each other. The first end has a first flange expanding outward. The first flange is welded to a pad of a substrate by a solder. An included angle between an extension direction of the first flange and a length direction of the terminal base is greater than 90 degrees.

Power semiconductor device

This disclosure relates to a combined power module that includes a base structure, a terminal structure, a second terminal, and a cover. The terminal structure includes a mount assembly and a plurality of first terminals. The mount assembly is assembled on the base structure. The first terminals are disposed on the mount assembly. The second terminal is disposed on the base structure. The cover is disposed on the base structure and covers at least part of the first terminals and at least part of the second terminal.

Combined power module

A chip package including a heat-dissipating device, a first thermal interface material layer disposed on the heat-dissipating device, a patterned circuit layer disposed on the first thermal interface material layer, a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer, and an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer is provided. The first thermal interface material layer has a thickness between 100 &#x3bc;m and 300 &#x3bc;m. The first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device.

Chip package

A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.

An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material. A maximum thickness of the intermetallic compound disposed between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material is greater than the thickness of the intermetallic compound disposed between the electronic device and the conductive layer.

Electronic packaging structure

A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.

Semiconductor package structure

A chip packaging includes a substrate, a first chip, a molding material, a first circuit, and a second circuit. The substrate includes a bottom surface, a first top surface disposed above the bottom surface with a first height, and a second top surface disposed above the bottom surface with a second height. The first height is smaller than the second height. The first chip is disposed on the first top surface. The molding material is disposed on the substrate and covers the first chip. The first and second circuits are disposed on the molding material, and are respectively and electrically connected to the first chip and the second top surface of the substrate. The substrate is made of copper material with huge area and has the properties of high current withstand capacity and high thermal efficiency. The second top surface protects the first chip from damage.

Chip packaging and composite system board

A solder and a solder joint structure formed by the solder are provided. The solder includes a zinc-based material, a copper film, and a noble metal film. The copper film completely covers the surface of the zinc-based material. The noble metal film completely covers the copper film. The solder joint structure includes a zinc-based material and an intermetallic layer. The intermetallic layer consists of zinc and noble metal and completely covers the surface of the zinc-based material.

Solder, solder joint structure and method of forming solder joint structure

A method of fabricating a circuit board is provided. An elastic bump material layer is formed on a substrate and then is patterned to form a plurality of first elastic bumps and a plurality of second elastic bumps, arranged in at least an array. A conductive layer is formed and then is patterned to form a patterned circuit layer to cover first plurality of elastic bumps and a portion of the substrate. An entirety of the plurality of second elastic bumps and another portion of the substrate are not covered by the patterned circuit layer. A protection layer is formed to cover a portion of the patterned circuit layer, a second number of the plurality of second elastic bumps entirely, a third number of the plurality of second elastic bumps partially and the another portion of the substrate, and expose the first number of the plurality of second elastic bumps.

Method of fabricating of circuit board

A base of circuit board, a circuit board, and a method of fabricating thereof are provided. The circuit board includes a substrate, a plurality of elastic bumps and a patterned circuit layer. The elastic bumps arranged in at least an array are located on the substrate. The patterned circuit layer is located on a portion of the elastic bumps and a portion of the substrate. The base of the circuit board and the method of fabricating thereof are also included in the present invention.

Base for circuit board, circuit board, and method of fabricating thereof

An electrical connecting structure including a conductive pad, a polymer bump and a patterned conductive layer is provided. The conductive pad is on a substrate and the polymer bump is disposed over the substrate. The patterned conductive layer is disposed on the polymer bump and electrically connects to the conductive pad, wherein the patterned conductive layer covers a portion of the polymer bump and exposes another portion of the polymer bump.

Growing community of inventors

Hsinchu, Taiwan

Kuo-Shu Kao