Taiwan Semiconductor Manufacturing Comp. Ltd.

Realtek Semiconductor Inc.

Kuo-Nan Yang

Chung-Hsing Wang

Chin-Shen Lin

Hiranmay Biswas

Yi-Chuin Tsai

Wan-Yu Lo

Chou-Kun Lin

Chien-Ju Chao

Jerry Chang-Jui Kao

Sheng-Hsiung Chen

Meng-Xiang Lee

Chenming Hu

Chih-Liang Chen

Po-Hsiang Huang

Hui-Zhong Zhuang

Fu-Liang Yang

Jung-Chan Yang

Nitesh Katta

Jack Liu

Lee-Chung Lu

Yi-Kan Cheng

Hou-Yu Chen

Chun-Chen Chen

Chi-Yeh Yu

Ting-Wei Chiang

Fong-Yuan Chang

Ming-Hsien Lin

Yen-Hung Lin

Shao-Huan Wang

Kuang-Ching Chang

Chung-hsing Wang

Hao-Tien Kan

Yi-Ling Chan

Aftab Alam Khan

Sheng-Fong Chen

Wei-Yu Chen

Ta-Pen Guo

Jerry Chang Jui Kao

Ming-Hsiang Song

Hsiang-Jen Tseng

King-Ho Tam

John Jianghann Lin

You-Lin Chu

Yee-Chia Yeo

Chun-Chieh Lin

Chien-Chao Huang

Cheng-I Huang

Kumar Lalgudi

Sheng-hsiung Chen

Yu-Jen Chang

Stefan Rusu

Shao-huan Wang

Haur-Ywh Chen

Ren-Zheng Liao

Jhih-Hong Ye

Yi-Lang Chen

Yen-Hsu Shih

Dian-Hau Chen

Chin-Chou Liu

Chi-Yu Lu

Hsiang-Ku Shen

Huang-Yu Chen

Kai-Wen Cheng

Shieh-Hsing Kuo

Chih-Hung Wu

Shyh-Horng Yang

Fang-Cheng Chen

Jhong-Sheng Wang

Zhe-Wei Jiang

Chung-Kai Lin

Min-Yuan Tsai

Ting-Wei Chang

Fang-Yu Fan

Shu-Yi Ying

Shou-En Liu

Li-Han Liang

Cheng-Yu Lin

Tan-Li Chou

Chia-Hua Hsu

Jerry Kao

Chia-Ying Chiu

Yeh-Chi Chang

Tao-Chun Wang

Yan-Shen You

Yi-Ling Chang

Fong-Ray Gu

Jui-Jung Hsu

Ritesh Kumar

Jia Han Lin

A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure comprises a first semiconductor device, a second semiconductor device, and a first semiconductor component. The first semiconductor device and the second semiconductor device defining a channel region. The first semiconductor component is disposed in the channel region and configured to control states of a plurality of components in the channel region. The first semiconductor device and the first semiconductor component are located adjacent to a boundary, and the first semiconductor component is electrically isolated from the first semiconductor device.

Semiconductor structure including boundary header cell and method for manufacturing the same

A logic cell structure includes a first portion, a second portion and a third portion. The first portion, arranged to be a first layout of a first semiconductor element, is placed in a first cell row of a substrate area extending in a first direction. The second portion, arranged to be a second layout of a second semiconductor element, is placed in a second cell row of the substrate area. The third portion is arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element. The first, second and third portions are bounded by a bounding box with a height in a second direction and a width in the first direction. Respective centers of the first portion and the second portion are arranged in a third direction different from each of the first direction and the second direction.

Logic cell structure and integrated circuit with the logic cell structure

An integrated circuit includes a device, a first interconnect structure disposed above the device and a second interconnect structure positioned below the device. The first interconnect structure includes multiple frontside metal layers. The second interconnect structure includes multiple backside metal layers, where each backside metal layer includes metal conductors routed according to diagonal routing. In some embodiments, a backside interconnect structure can include another backside metal layer that includes metal conductors routed according to mixed-Manhattan-diagonal routing. A variety of techniques can be used to route signals between metal conductors in the backside interconnect structure and cells on one or more frontside metal layers.

Diagonal backside power and signal routing for an integrated circuit

A method of forming an integrated circuit includes forming at least a first or a second set of devices in a substrate, forming an interconnect structure over the first or second set of devices, and depositing a set of conductive structures on the interconnect structure. The first and second set of devices are configured to operate on a first supply voltage. Forming the interconnect structure includes depositing a set of insulating layers over the first or second set of devices, etching the set of insulating layers thereby forming a set of trenches, depositing a conductive material within the set of trenches, thereby forming a set of metal layers, and forming a portion of a header circuit between a first and a second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices.

Integrated circuit and method of forming the same

An integrated circuit includes a first power rail on a back-side of a wafer and being configured to supply a first voltage, a header circuit coupled to the first power rail and being configured to supply the first voltage to the first power rail, a second and third power rail on the back-side of the wafer, a fourth power rail on a front-side of the wafer, and a fifth power rail on the back-side of the wafer. The second and third power rail being configured to supply a second voltage. The fourth power rail includes a first set of conductors configured to supply a third voltage to the header circuit. The fifth power rail is configured to supply the third voltage and is separated from the first power rail in a first and second direction, and is separated from the second and third power rail in the first direction.

An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.

Systems and methods for integrated circuit layout

A conductive line structure includes: first and second offset sets of long pillars that are substantially coaxial on an intra-set basis; a third set of offset short pillars, the short pillars being: overlapping of long pillars in the first and second sets; and organized into groups of first quantities of the short pillars; each of the groups being overlapping of and electrically coupled between a pair of one of the long pillars in the first set and a one of the long pillars in the second set such that, in each of the groups, each short pillar being overlapping of and electrically coupled between the pair; and each long pillar in each of the first and second sets being overlapped by a second quantity of short pillars in the third set and being electrically coupled to same; and the first quantity being less than the second quantity.

Conductive line structures and method of forming same

One aspect of this description relates to an integrated circuit (IC) structure including a first layer and a second layer. The first layer includes a first metal structure coupled to a first power supply having a first voltage level and a second metal structure coupled to a second power supply having a second voltage level different from the first voltage level. The second layer is formed over the first layer. The second layer includes a first nano-sheet device coupled to the first metal structure and a second nano-sheet device adjacent to the first nano-sheet device. The second nano-sheet device is coupled to the second metal structure. A distance between the first nano-sheet device and the second nano-sheet device is less than a minimum n-well to n-well spacing.

Multiple power domains using nano-sheet structures

A method of forming a semiconductor arrangement includes forming a first capacitor in a first voltage domain and forming a second capacitor in the first voltage domain. The first capacitor is connected in parallel with the second capacitor. A third capacitor and a fourth capacitor are formed in a second voltage domain. The third capacitor is connected in series with the fourth capacitor. The first capacitor and the second capacitor are connected in parallel with a supply terminal of the first voltage domain and a reference terminal of the first voltage domain. The fourth capacitor is connected to a supply terminal of the second voltage domain. The third capacitor is connected to a reference terminal of the second voltage domain.

Semiconductor arrangement and method of making

A device includes a power grid (PG) arrangement including: first and second segments in a first conductive layer which are conductive and extend in a first direction, the first segments being configured for a first reference voltage and the second segments being configured for a second reference voltage; the first and second segments being interspersed relative to a second direction, the second direction being perpendicular to the first direction; and relative to the second direction, the first segments being symmetrically spaced apart relative to each other, the second segments being symmetrically spaced apart relative to each other, and the second segments being substantially asymmetrically spaced between corresponding adjacent ones of the first segments.

Semiconductor device including standard-cell-adapted power grid arrangement

Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate, a power switch, a first power mesh and a second power mesh. The power switch is formed over the front surface of the semiconductor substrate. The first power mesh is formed over the power switch and is directly connected to the first terminal of the power switch. The second power mesh is formed over the back surface of the semiconductor substrate and is directly connected to the second terminal of the power switch.

Semiconductor device including frontside power mesh and backside power mesh and manufacturing method thereof

A semiconductor device including a first oxide definition (OD) strip doped by a first-type dopant in a first doping region defining an active region of a first Metal-Oxide Semiconductor (MOS); a second OD strip doped by a second-type dopant in a second doping region and a third doping region, the second doping region defining an active region of a second MOS and the third doping region defining a body terminal of the first MOS, wherein the second OD is parallel to the first OD strip; and a first dummy OD strip, wherein a boundary between the second doping region and the third doping region is formed over the first dummy OD strip; wherein the first-type dopant is different from the second-type dopant.

Semiconductor device

A method of manufacturing a semiconductor device includes forming a set of cells; forming a PG layer, including forming a first metallization layer including forming first conductor portions and second conductor portions, corresponding ones of the first conductor portions being arranged in first pairs; corresponding ones of the second conductor portions being arranged in second pairs; the cells being arranged to overlap at least one of the first and second conductor portions of the first metallization layer relative to the first direction; and forming a second metallization layer over the first metallization layer, the second metallization layer including forming third conductor portions and fourth conductor portions, the cells being arranged in a repeating relationship that each cell overlaps, an intersection of a corresponding one of the first or second pairs with at least a corresponding one of the third conductor portions or a corresponding one of the fourth conductor portions.

Method of manufacturing a semiconductor device including PG-aligned cells

Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.

Layouts for conductive layers in integrated circuits

A method (of generating a revised layout diagram of a conductive line structure for an IC) including: for a first set of pillar patterns that represents portions of an M(i) layer of metallization and where i is a non-negative number, the first set including first and second pillar patterns which extend in a first direction, are non-overlapping of each other with respect to the first direction, are aligned with each other and have a first distance of separation, determining a first distance of separation as between corresponding immediately adjacent members of the first set; recognizing that the first distance is less than a transverse routing (TVR) separation threshold for an M(i+j) layer of metallization, where j is an integer and j≥2; and increasing the first distance so as to become a second distance which is greater than the TVR separation threshold of the M(i+j) layer.

Method of forming merged pillar structures and method of generating layout diagram of same

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Hsinchu, Taiwan

Kuo-Nan Yang