Worldwide Semiconductor Manufacturing Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Nanodynamics, Inc.

National Synchrotron Radiation Research Center

Kung Linliu

Mai-Ru Kuo

Yeur-Luen Tu

Hua-Tai Lin

Ming-Hsun Yang

Wan-Yih Lien

Chih-Chieh Hsu

Guey-Chyuan Chen

Meng-Jaw Cherng

Wan Yih Lien

Arnold Chang-mou Yang

Yi-Ren Huang

Shin-Pu Jeng

Chunshing Chen

Bor-Wen Chan

The present invention discloses a package structure of an inkjet-printhead chip. The structure includes: a nozzle structure of a print element including an ink chamber layer, a nozzle base layer on the ink chamber layer, and a nozzle layer on the nozzle base layer, wherein a plurality of nozzle through holes are set in the nozzle layer and pass through an ink chamber of the ink chamber layer; a flexible substrate set on the nozzle layer, wherein there is at least an opening set in the flexible substrate to expose those nozzle through holes; and a chip set under the ink chamber layer. Besides, the present package method is to utilize the micro-manufacturing process to form the nozzle structure of a print element and the tape automatic bonding process to bond the flexible substrate on the nozzle layer and the chip under the ink chamber layer.

Package structure of inkjet-printhead chip

The present invention discloses a package method of the inkjet-printhead chip and its structure. The structure includes: a nozzle structure of a print element including an ink chamber layer and a nozzle layer on the ink chamber layer, wherein a plurality of nozzle through holes are set in the nozzle layer and pass through an ink chamber of the ink chamber layer; a flexible substrate set on the nozzle layer, wherein there is at least an opening set in the flexible substrate to expose those nozzle through holes; and a chip set under the ink chamber layer. Besides, the present package method is to utilize the micro-manufacturing process to form the nozzle structure of a print element and the tape automatic bonding process to bond the flexible substrate on the nozzle layer and the chip under the ink chamber layer.

Package method of inkjet-printhead chip and its structure

A self-aligned fabrication process for a nozzle plate of an inkjet print head. A substrate is provided with an activated device and a first film is formed on the substrate. Then, a second film is formed on the first film. Next, the second film is defined to form a convex portion corresponding to the activated device, exposing a part of the surface of the first film. Next, a third film is formed on the exposed surface of the first film, covering the convex portion. The third film on the convex portion is then removed. Next, the convex portion and the first film under the convex portion are etched to form a via.

Self-aligned fabrication process for a nozzle plate of an inkjet print head

A method of forming a nozzle plate of an inkjet print head. A silicon chip is provided with an activated device and a first film is formed on the silicon chip, with a first opening corresponding to the activated device. Then, a second film is formed on the first film. Next, a photoresist layer is formed on the second film, such that the photoresist layer has a second opening corresponding to the first opening. Next, the second film under the second opening of the photoresist layer is etched to form a via in the second film passing through the first opening.

Method of using photolithography and etching for forming a nozzle plate of an inkjet print head

A method for fabricating a via openings, comprising the following steps. A semiconductor structure is provided. A low-k layer is formed upon the semiconductor structure. A via opening is formed within the low-k layer. An inert polymer liner layer is formed upon the low-k layer and within the via opening. A photoresist layer is formed upon the inert polymer liner layer, filling the inert polymer lined via opening. The inert polymer liner layer preventing adverse chemical reactions between the photoresist layer and portions of the low-k layer. The photoresist layer is patterned to expose the inert polymer lined via opening and portions of the inert polymer lined low-k layer adjacent the via opening. The exposed inert polymer lined via opening and portions of the inert polymer lined low-k layer adjacent the via opening and the portions of the inert polymer liner layer upon the via opening and portions of the inert polymer lined low-k layer adjacent the via opening are etched to form a structure opening. The patterned photoresist layer is removed. The structure is cleaned and a planarized metal structure is formed within the structure opening.

Method to prevent poison via

A method of forming an anti-reflective coating is described. A film is formed on a substrate. A first layer of an anti-reflective coating layer Is deposited on the film by chemical vapor deposition using a canrier gas, an organic halide gas and a hydrogen halide gas as gas sources. A second layer of the anti-reflective coating layer is formed on the first layer of the anti-reflective coating layer by chemical vapor deposition using a carrier gas and an organic halide gas as gas sources. A photoresist layer is formed on the second layer of the anti-reflective coating layer.

Method of forming a dual-layer anti-reflective coating

A method of manufacturing dynamic random access memory (DRAM) capacitor. A semiconductor substrate having an insulation layer thereon is supplied. A triblock copolymer layer is formed over the insulation layer by performing a spin-coating process. The triblock copolymer layer is patterned and then the triblock copolymer layer is annealed at a low temperature. The annealed triblock copolymer is exposed to ultraviolet rays in an atmosphere containing ozone so that the triblock copolymer is converted into a lower electrode layer having a bicontinuous three-dimensional nanoporous structure. A dielectric layer is formed over the lower electrode. An upper electrode is formed over the dielectric layer. The upper electrode, the dielectric layer and the lower electrode are sequentially patterned to form the DRAM capacitor. The lower electrode made from bicontinuous ceramic material is able to allow for greater surface area and hence is suitable for forming the capacitors in a DRAM unit with storage capacity of 64 MB or more.

Method of manufacturing semiconductor capacitor

A method of fabricating bit lines is described. A semiconductor substrate has isolation structures formed therein. Gate structures are formed over the semiconductor substrate. Each gate structure comprises a conducting gate layer and a cap layer on the conducting gate layer. A common source and a drain is formed in the semiconductor substrate. A spacer is formed on the sidewall of each gate structure. A dielectric layer is formed over the semiconductor substrate. The dielectric layer is patterned to form bit line contact holes and bit line trenches, wherein the bit line contact holes expose the common sources, and the bit line trenches expose a part of the cap layer and a part of the isolation structures. The bit line contact holes and the bit line trenches are filled with a conducting layer; consequently, bit line contacts and patterned bit lines are formed.

Method of fabricating bit lines

A method for forming organic anti-reflective coating (ARC) is disclosed in the present invention. A substrate is provided and an ARC is deposited on the substrate using reactive gas. The reactive gas comprising compound gas containing carbon atom, hydrogen atom and halogen atom, where said compound gas has a general formula of C,H,X,, X is halogen element, x ranges from 0 to 5, y ranges from 0 to 9 and z ranges from 0 to 9. The reactive gas could be injected into a chamber with carrier gas, which is helium gas or argon gas.

Method for forming bottom anti-reflective coating (BARC)

The present invention discloses a method for forming a self-aligned contact hole, which provides a large process window and ensures full utilization of bottom contact area even when the overlay is not well aligned. The method comprises the steps of (a) providing a semiconductor substrate having a gate electrode and a diffusion region thereon; (b) forming a conformal layer of etch barrier material overlying the substrate surface including the diffusion region and the upper surface and the sidewalls of the gate electrode; (c) forming an insulating layer overlying the barrier layer; (d) forming a mask layer overlying the insulating layer; (e) etching an opening through the mask layer and part of the way through the insulating layer, aligned with the diffusion region, until the barrier layer is exposed; (f) forming spacers on the sidewalls of the opening; (g) removing the remaining portion of the insulating layer underneath the opening by isotropically etching using mask layer, spacers and barrier layer as stopping layers; and (h) removing the barrier layer underneath the opening, thereby exposing the diffusion region.

Self-aligned contact process

A device and method for planarizing a film layer device on a silicon wafer. The device has a circular track whose surface faces the track center, a carrier capable of moving along the track and carrying wafers around with their front surfaces facing the center, and a set of heating elements for heating the film layers on the wafers to make them fluid. Utilizing the centrifugal force on the film layer generated by the circular movement and the fluidity of the film layer provided by heating, planarization of the film layer is achieved.

Device and method for planarizing a thin film

A multiple crown capacitor and a method of fabricating such a capacitor is described. The method is applicable to a substrate in which an isolation layer is formed on the substrate, with a node contact plug formed in the isolation layer. A sacrificial layer is then formed on the substrate followed by a patterning of the sacrificial layer to form a succession of openings above the node contact plug and its surroundings, exposing the isolation layer and a portion of the node contact plug upper surface. Thereafter, a conformal conductive layer is formed on the sacrificial layer and in the openings. A portion of the conductive layer, which is higher than the sacrificial layer, is removed, followed by removing the sacrificial layer to form a bottom electrode. A conformal dielectric layer and an upper electrode are sequentially formed on the bottom electrode to complete the formation of the capacitor. The structure of the capacitor includes a bottom electrode, which comprises a succession of openings on the upper surface of the bottom electrode. The bottom electrode is located on the node contact plug and is electrically connected to the node plug. A conformal dielectric layer and an upper electrode are sequentially formed on the bottom electrode.

Structure and fabrication method for multiple crown capacitor

A method for fabricating a capacitor is described. A dielectric layer and a polysilicon layer thereon are provided. A patterned oxide layer and spacers on the sidewalls of the patterned oxide layer are formed. The polysilicon layer is etched using the oxide layer and spacer as an etching mask. The oxide layer and spacer are then removed. A dielectric layer and a conductive layer are sequentially formed on the polysilicon layer.

Method for fabricating capacitor

A method for manufacturing dynamic random access memory (DRAM) capacitor. A first insulation layer having a plurality of first plugs and second plugs therein is formed over a substrate. A plurality of bit lines is formed over the first insulation layer. Each bit line has a multiple of bit line contacts, and each bit line contact is connected electrically to one of the first plugs. A cap layer is formed on top of the bit lines and spacers are formed on the sidewalls of the bit lines. The spacers are formed in such a way that they are linked near the bit line contact of every pair of neighboring bit lines. A planarized second insulation layer is formed over the substrate. Using the cap layers, the spacers and the second plugs as stopping points, an etching operation is carried out to form the lower electrode openings of capacitors and node contact openings. A conformal conductive layer that covers the exposed surfaces of the electrode openings and the node contact openings are formed, hence forming the lower electrode of a capacitor. A dielectric layer is formed over the lower electrode, and finally an upper electrode is formed over the dielectric layer to form a complete capacitor.

Method for manufacturing DRAM capacitor

A method of forming a bottom storage node of a DRAM capacitor over a contact plug is disclosed. The method comprises the steps of: depositing an oxide layer over the contact plug; etching the oxide layer using a first photoresist layer having with a first masking pattern, the first masking pattern allowing the removal of the oxide layer over the contact plug; depositing a polysilicon layer over the oxide layer and in electrical contact with the contact plug; forming a second photoresist layer having a second masking pattern onto the polysilicon layer, the second masking pattern being substantially similar to the first masking pattern, but rotated by a predetermined angle; and etching the polysilicon layer in accordance with the second photoresist layer until the oxide layer is reached.

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