Yangtze Memory Technologies Co., Ltd.

Central China Normal University

Kun Zhang

Wenxi Zhou

Zhiliang Xia

Zongliang Huo

Linchun Wu

Yuancheng Yang

Zhong Zhang

Lei Liu

Wei Liu

Liang Chen

Yanhong Wang

Di Wang

Tao Yang

ZongLiang Huo

DongXue Zhao

Kun Bao

Zhongwang Sun

Cuicui Kong

Haojie Song

Shan Li

Ziqun Hua

Cheng Gan

Rui Su

Yuhui Han

Dongxue Zhao

Yanwei Shi

Guangji Li

Jianzhong Wu

Wei Xie

Bingguo Wang

Jiwei Cheng

Tingting Zhao

Ming Hu

Shijin Luo

Fandong Liu

Zongkai Yang

Shiqi Huang

Zhicheng Dai

Changzhi Sun

Jingying Chen

Sannvya Liu

Dongyu Fan

Yaqin Liu

Ruyi Xu

Leyuan Liu

Shixin Peng

A three-dimensional (3D) memory device is disclosed. The 3D memory device includes a memory stack, a semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack, and a source contact above the memory stack and in contact with the semiconductor layer. A semiconductor plug, in contact with the semiconductor layer, surrounds an end of one of the channel structures. The source contact is electrically connected with the one of the channel structures. At least a portion of the source contact is buried within the semiconductor layer.

Three-dimensional memory devices

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor. The first peripheral circuit is between the first bonding interface and the second semiconductor layer. The third semiconductor layer is between the second peripheral circuit and the second bonding interface.

Three-dimensional memory devices and methods for forming the same

A memory device includes an array of memory cells disposed on a first side of a first semiconductor layer, and a peripheral circuit bonded to the array of memory cells. Each of the memory cells includes a semiconductor body extending in a first direction, a first terminal and a second terminal are formed at both ends of the semiconductor body; a word line extending in a second direction perpendicular to the first direction; plate lines extending in the second direction; and a first dielectric layer disposed between the semiconductor body and the word line and the plate line.

Memory devices and methods for forming the same

A semiconductor device includes an insulating layer, a conductive layer stacking with the insulating layer and including a first conductive sublayer and a second conductive sublayer, a memory stack disposed on a side of the conductive layer away from the insulating layer, a spacer structure through the conductive layer, a contact structure in the spacer structure and extending vertically through the insulating layer, and a channel structure including a semiconductor channel. The contact structure includes a first contact portion and a second contact portion in contact with each other. A lateral cross-sectional area of the second contact portion is greater than a lateral cross-sectional area of the first contact portion. A portion of the semiconductor channel is in contact with the first conductive sublayer. The second conductive sublayer is disposed between the first conductive sublayer and the memory stack.

Semiconductor device including a memory stack and a contact structure in a spacer structure

A 3D memory device includes a conductor/insulator stack containing a conductive layer and a dielectric layer alternatingly stacked, channel hole structures in a first region of memory cells in the conductor/insulator stack, a blocking structure adjacent to the first region, and a dummy channel hole structure in the first region. The dummy channel hole structure is adjacent to the blocking structure, and includes a dielectric material that fills a channel hole to form a first dielectric filling structure.

Three-dimensional memory device and fabrication method for improved yield and reliability

Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. In certain aspects, a disclosed 3D memory device can comprise a first semiconductor structure including a core region, a staircase region, and a periphery region, and a second semiconductor structure including a second periphery circuit on a substrate. The first semiconductor structure can include a memory stack on an activated semiconductor layer in the core region, a staircase structure on a supplemental semiconductor layer in the staircase region, and a first periphery circuit on a doped semiconductor film in the periphery region. The second semiconductor structure is connected with the first semiconductor structure.

Three-dimensional memory devices and fabricating methods thereof

A semiconductor device semiconductor device includes a stack having a first surface and a second surface opposing the first surface. The stack can include word line layers and insulating layers alternating with the word line layers between the first surface and the second surface. The stack can further include a process stop layer between the lower most insulating layer and the second surface. The stack can extend along an X-Y plane having an X direction and a Y direction perpendicular. The semiconductor device can further include a slit structure crossing the stack between the first surface and the second surface in Z direction. In a cross-section perpendicular to the Y direction, distances between the slit structure and the process stop layer at two sides of the slit structure are each larger than distances at either side of the slit structure between the word line layers and the slit structure.

Three-dimensional NAND memory device having word line contact with dielectric filler

A method of fabricating a three-dimensional (3D) memory device includes forming a stack structure on a substrate, forming a channel structure, a dummy channel structure, and a gate line slit structure penetrating through the stack structure and extending into the substrate, removing the substrate to expose a first side of the stack structure, forming a protective layer covering an exposed portion of the channel structure on the first side of the stack structure, removing at least the exposed portion of the channel structure, and removing the protective layer after removing at least the exposed portion of the channel structure.

Fabrication method of three-dimensional memory device

Three-dimensional memory devices and fabricating methods therefore are disclosed. The memory device can comprise a stack structure comprising a plurality of gate layers, a plurality of first insulating layers, and a plurality of second insulating layers. The stack structure has a staircase region comprising a plurality of stair structures. Each stair structure comprises a first portion of the stair structure comprising one gate layer and a first portion of one first insulating layer, and a second portion of the stair structure comprising a second portion of the one first insulating layer and a second insulating layer. The memory device can further comprise at least one contact structure each located on a top surface of one of the plurality of stair structures, and at least one contact portion in contact with the at least one contact structure.

Three-dimensional memory devices with stack structures, and fabricating methods thereof

Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. A channel hole is formed in a stack including alternating first layers and second layers. The stack is formed over a substrate of the semiconductor device. A gate dielectric layer and a channel layer are sequentially formed in the channel hole. Laser annealing is performed on the channel layer using laser light. An incidence angle of the laser light on an upper surface of the channel layer causes a total internal reflection to occur at an interface between the channel layer and the gate dielectric layer and an interface between the channel layer and an insulating layer that is adjacent to the channel layer.

Method of fabricating a semiconductor device using laser annealing

A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a first angled structure, and a first diameter of the memory film at the bottom portion below the first angled structure is smaller than a second diameter of the memory film at an upper portion above the first angled structure.

Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a first semiconductor assembly, a second semiconductor assembly, and an inter-assembly bonding layer between the first semiconductor assembly and the second semiconductor assembly. The first semiconductor assembly includes a first array structure and a first periphery structure. The first array structure includes a first memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The first periphery structure includes a plurality of first peripheral circuits electrically connected to the first memory stack. The second semiconductor assembly includes a second array structure and a second periphery structure. The second array structure includes a second memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The second periphery structure includes a plurality of second peripheral circuits electrically connected to the second memory stack.

Three-dimensional memory devices having semiconductor assemblies bonded by bonding layer and methods for forming the same

Embodiments of three-dimensional memory devices are disclosed. A disclosed memory structure can comprises a memory cell, a bit line contact coupled to the memory cell, a bit line coupled to the bit line contact, a source line contact coupled to the memory cell, and a source line coupled to the source line contact. The memory cell comprises a cylindrical body having a cylindrical shape, an insulating layer surrounding the cylindrical body, a word line contact surrounding a first portion of the insulating layer, the word line contact coupled to a word line, and a plurality of plate line contact segments surrounding a second portion of the insulating layer, the plurality of plate line contact segments coupled to a common plate line.

Three-dimensional memory devices having a cylindrical body and plate line contact segments

A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact coupled to a word line, a second gate contact coupled to a plate line, and an annular dielectric layer within a portion of the pillar. The annular dielectric layer can increase a retention time of electrical charge in the pillar. The 3D memory device can utilize dynamic flash memory (DFM), increase retention times, decrease refresh rates, increase a floating body effect, decrease manufacturing defects, decrease leakage current, decrease junction current, decrease power consumption, increase an upper limit of charge density in the pillar, dynamically adjust a length of the plate line, and decrease parasitic resistance.

Dynamic flash memory (DFM) with ring-type insulator in channel for improved retention

A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer. A first thickness of the bottom portion of the channel structure is larger than a second thickness of a top portion of the channel structure.

Growing community of inventors

Wuhan, China

Kun Zhang