Taiwan Semiconductor Manufacturing Comp. Ltd.

Kun-Tsang Chuang

Gulbagh Singh

Hsin-Chi Chen

Tsung-Han Tsai

Chiang-Ming Chuang

Po-Jen Wang

Hung-Che Liao

Chih-Ming Lee

Yung-Lung Hsu

Chih-Hsun Lin

Chia-Yi Tseng

Wang Po-Jen

Chien-Hsuan Liu

Shih-Lu Hsu

Kuan-Liang Liu

Yen-Hsung Ho

Wei-Chung Lu

Yu-Chu Lin

Chia-Ming Pan

Ping-Pang Hsieh

Kuan-Wei Su

Chia Hsing Huang

Wei-Ting Chen

Yong-Shiuan Tsair

Po-Wei Liu

Ying-Hao Chen

Jyun-Guan Jhou

Szu-Hsien Lu

Chien-Cheng Huang

Yu-Shih Lin

A transistor device and method of making the same are disclosed. The transistor device includes one or more air gaps in one or more sidewall spacers. The one or more air gaps may be located adjacent the gate and/or above the source or drain regions of the device. Various embodiments may include different combinations of air gaps formed in one or both sidewall spacers. Various embodiments may include air gaps formed in one or both sidewall spacers adjacent to the gate and/or above the source or drain regions of the device. The formation of the air gaps may reduce unwanted parasitic and/or fringing capacitance.

MOSFET device structure with air-gaps in spacer and methods for forming the same

A semiconductor arrangement includes a gate structure disposed between a first source/drain region and a second source/drain region and a first contact disposed over the first source/drain region. The semiconductor arrangement includes a second contact disposed over the second source/drain region and an airgap disposed between the first contact and the second contact and over the gate structure.

Semiconductor arrangement with airgap and method of forming

A circuit includes a base silicon layer, a base oxide layer, a first top silicon layer, a second top silicon layer, a first semiconductor device, and a second semiconductor device. The base oxide layer is formed over the base silicon layer. The first top silicon layer is formed over a first region of the base oxide layer and has a first thickness. The second top silicon layer is formed over a second region of the base oxide layer and has a second thickness less than the first thickness. The first semiconductor device is formed over the first top silicon layer and the second semiconductor device is formed over the second top silicon layer. The ability to fabricate a top silicon layers with differing thicknesses can provide a single substrate having devices with different characteristics, such as having both fully depleted and partially depleted devices on a single substrate.

Semiconductor wafer with devices having different top layer thicknesses

The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.

Reducing RC delay in semiconductor devices

A semiconductor structure includes a substrate assembly and a semiconductor device. The semiconductor device is formed on the substrate assembly, and includes a body region, two active regions, and a butted body. The active regions are disposed at two opposite sides of the body region, and both have a first type conductivity. The body region and the active regions together occupy on a surface region of the substrate assembly. The butted body has a second type conductivity different from the first type conductivity, and is located on the surface region of the substrate assembly so as to permit the body region to be tied to one of the active regions through the butted body.

Semiconductor structure and method for manufacturing the same

A semiconductor device may include a source on a first side of a gate. The semiconductor device may include a drain on a second side of the gate, where the second side of the gate is opposite to the first side of the gate. The semiconductor device may include a first contact over the source. The semiconductor device may include a second contact over the drain. The semiconductor device may include an air gap over the gate between at least the first contact and the second contact. The semiconductor device may include at least two dielectric materials in each of a region between the air gap and the first contact and a region between the air gap and the second contact.

Method of manufacturing a metal-oxide-semiconductor field-effect transistor (MOSFET) having low off-state capacitance

A semiconductor device includes a substrate, a gate oxide layer formed on the substrate, a gate formed on the gate oxide layer, and a spacer formed adjacent the gate and over the substrate. The spacer includes a void filled with air to prevent leakage of charge to and from the gate, thereby reducing data loss and providing better memory retention. The reduction in charge leakage results from reduced parasitic capacitances, fringing capacitances, and overlap capacitances due to the low dielectric constant of air relative to other spacer materials. The spacer can include multiple layers such as oxide and nitride layers. In some embodiments, the semiconductor device is a multiple-time programmable (MTP) memory device.

Semiconductor device with air-void in spacer

The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.

Source/drain epitaxial layer profile

Semiconductor-on-insulator (SOI) field effect transistors (FETs) including body regions having different thicknesses may be formed on an SOI substrate by selectively thinning a region of a top semiconductor layer while preventing thinning of an additional region of the top semiconductor layer. An oxidation process or an etch process may be used to thin the region of the top semiconductor layer, and a patterned oxidation barrier mask or an etch mask may be used to prevent oxidation or etching of the additional portion of the top semiconductor layer. Shallow trench isolation structures may be formed prior to, or after, the selective thinning processing steps. FETs having different depletion region configurations may be formed using the multiple thicknesses of the patterned portions of the top semiconductor layer. For example, partially depleted SOT FETs and fully depleted SOI FETs may be provided.

Multiple thickness semiconductor-on-insulator field effect transistors and methods of forming the same

A method of making a semiconductor structure includes depositing a first passivation material between adjacent conductive elements on a substrate, wherein a bottommost surface of the first passivation material is coplanar with a bottommost surface of each of the adjacent conductive elements. The method further includes depositing a second passivation material on the substrate, wherein the second passivation material contacts a sidewall of each of the adjacent conductive elements and a sidewall of the first passivation material, a bottommost surface of the second passivation material is coplanar with the bottommost surface of each of the adjacent conductive elements, and the second passivation material is different from the first passivation material.

Method of making a semiconductor structure

Method of manufacturing a metal-oxide-semiconductor field-effect transistor (MOSFET) having low off-state capacitance due to reduction of off-state capacitance of back-end-of-line (BEOL) features of the MOSFET

Growing community of inventors

Miaoli, Taiwan

Kun-Tsang Chuang